2nd Generation Intel® Core™ Processor Family Desktop, Intel® Pentium® Processor Family Desktop, and Intel® Celeron® Processor Family Desktop Datasheet, Volume 2 Supporting: Intel® Core™ i7, i5 and i3 Desktop Processor Series Intel® Pentium® G800 and G600 Desktop Processor Series Intel® Celeron® G500 and G400 Desktop Processor Series This is Volume 2 of 2

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Revision History Revision Number Revision Date January 2011 Initial release Added Intel® Pentium® processor family desktop Updated DSTS-Device Status Register (B/D/F/Type: 0/1/0/PCI) Added four registers to Section 2.13, MCHBAR Registers in Memory Controller – Channel 0. Added four registers to Section 2.14, MCHBAR Registers in Memory Controller – Channel 1 Added Intel® Celeron® processor family desktop

Introduction This is Volume 2 of the Datasheet for the following products: • 2nd Generation Intel® Core™ processor family desktop • Intel® Pentium® processor family desktop • Intel® Celeron® processor family desktop The processor contains one or more PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on the PCI Bus assigned for the processor socket. This document describes these configuration space registers or device-specific control and status registers (CSRs) only. This document does NOT include Model Specific Registers...

Processor Configuration Registers Processor Configuration Registers This chapter contains the following: • Register terminology • PCI Devices and Functions on processor • System address map • Processor register introduction • Detailed register bit descriptions Register Terminology Table 2-1 shows the register-related terminology and register attributes that are used in this document. Attribute modifiers are listed in Table 2-2. Register Attributes and Terminology Item Read Only: These bits can only be read by software, writes have no effect. The value of the bits is determined by the hardware...

Processor Configuration Registers Register Attribute Modifiers Attribute Modifier Applicable Attribute Sticky: These bits are only re-initialized to their default value by a "Power Good Reset". Note: Does not apply to RO (constant) bits. Key: These bits control the ability to write other bits (identified with a 'Lock' modifier) Lock: Hardware can make these bits "Read Only" via a separate configuration bit or other logic. Note: Mutually exclusive with 'Once' modifier. Once: After reset, these bits can only be written by software once, after which they become "Read Only". Note: Mutually exclusive...

Processor Configuration Registers System Address Map The processor supports 512 GB (39 bit) of addressable memory space and 64 KB+3 of addressable I/O space. This section focuses on how the memory space is partitioned and what the separate memory regions are used for. I/O address space has simpler mapping and is explained near the end of this section. The processor supports PEG port upper prefetchable base/limit registers. This allows the PEG unit to claim I/O accesses above 32 bit. Addressing of greater than 4 GB is allowed on either the DMI Interface or PCI Express interface. The processor...

Processor Configuration Registers • Device 6, Function 0 — MBASE/MLIMIT – PCI Express port non-prefetchable memory access window. — PMBASE/PMLIMIT – PCI Express port prefetchable memory access window. — PMUBASE/PMULIMIT – PCI Express port upper prefetchable memory access window — IOBASE/IOLIMIT – PCI Express port I/O access window. • Device 2, Function 0 — IOBAR – I/O access window for internal graphics. Through this window address/data register pair, using I/O semantics, the IGD and internal graphics instruction port registers can be accessed. Note, this allows accessing the same registers as...

Processor Configuration Registers System Address Range Example PHYSICAL MEMORY (DRAM CONTROLLER VIEW) HOST/SYSTEM VIEW 512 GB PCI Memory Add. Range TOUUD BASE Reclaim Limit = Reclaim Base + x 1 MB aligned Reclaim BASE Main Memory Reclaim Add Range ME-UMA MESEG BASE Main memory Address Range Flash, APIC Intel TXT (20 MB) TSEG TSEG BASE Main Memory Add Range

Processor Configuration Registers Legacy Address Range This area is divided into the following address regions: • 0–640 KB – DOS Area • 640–768 KB – Legacy Video Buffer Area • 768–896 KB in 16 KB sections (total of 8 sections) – Expansion Area • 896–960 KB in 16 KB sections (total of 4 sections) – Extended System BIOS Area • 960 KB–1 MB Memory – System BIOS Area DOS Legacy Address Range 000F_FFFFh 000F_0000h 000E_FFFFh 000E_0000h System BIOS (Upper) 64 KB Extended System BIOS (Lower) 64 KB (16 KB x 4) 000B_FFFFh Legacy Video Area (SMM Memory) 128 KB 000A_0000h 0009_FFFFh DOS Range (0h–9_FFFFh)...

Processor Configuration Registers Legacy Video Area (A_0000h–B_FFFFh) The legacy 128 KB VGA memory range, frame buffer, (000A_0000h–000B_FFFFh) can be mapped to IGD (Device 2), to PCI Express (Device 1 or Device 6), and/or to the DMI Interface. The appropriate mapping depends on which devices are enabled and the programming of the VGA steering bits. Based on the VGA steering bits, priority for VGA mapping is constant. The processor always decodes internally mapped devices first. Non-SMM-mode processor accesses to this range are considered to be to the Video Buffer Area as described above. The...