2nd Gen Intel® Core? Processor Family Desktop Datasheet, Vol. 1
2nd Gen Intel® Core? Processor Family Desktop Datasheet, Vol. 1
This document is the first volume of a datasheet for the 2nd Generation Intel® Core™ Processor Family, including Intel® Pentium® and Intel® Celeron® processors for desktop systems. It provides detailed specifications and features for supported processor series such as Intel® Core™ i7, i5, i3, Pentium® G800/G600, and Celeron® G500/G400.
The datasheet outlines supported technologies, interfaces, power management, and thermal management. Key technologies include Intel® Virtualization Technology, Intel® Trusted Execution Technology, Hyper-Threading Technology, Turbo Boost Technology, and Advanced Vector Extensions.
The document details various interfaces such as System Memory Support, PCI Express, Direct Media Interface (DMI), and Platform Environment Control Interface (PECI). It also covers processor graphics and the Intel® Flexible Display Interface (FDI).
Power management features include support for Advanced Configuration and Power Interface (ACPI) states, processor core power management, and integrated memory controller states.
Technologies discussed include Intel® Virtualization Technology for IA-32, Intel® 64, and Directed I/O, Intel® Trusted Execution Technology, Hyper-Threading Technology, Turbo Boost Technology, Advanced Vector Extensions, and Advanced Encryption Standard New Instructions.
The document includes legal disclaimers regarding the use of Intel products, emphasizing that specifications are subject to change and that Intel assumes no liability for the use of its products in critical applications.
The document describes a desktop processor built on 32-nanometer process technology, designed for a two-chip platform with a processor and Platform Controller Hub (PCH). It highlights the processor's features, including an Integrated Display Engine, Processor Graphics, PCI Express ports, and an Integrated Memory Controller, all aimed at enhancing performance, reducing costs, and improving footprint.
The processor supports up to 12 Processor Graphics execution units and is available in an 1155-land LGA package. It includes four or two execution cores, with a 32-KB instruction and data first-level cache (L1) for each core, a 256-KB shared second-level cache (L2), and up to 8-MB shared third-level cache (L3).
The processor supports various technologies such as Intel Virtualization Technology, Intel Active Management Technology, Intel Trusted Execution Technology, Intel Hyper-Threading Technology, Intel Turbo Boost Technology, and Intel Advanced Encryption Standard New Instructions, among others.
The processor supports two channels of unbuffered DDR3 memory, PCI Express ports compliant with the PCI Express Base Specification, and a Direct Media Interface (DMI) with a 5 GT/s point-to-point interface to PCH. It also includes a Platform Environment Control Interface (PECI) and Processor Graphics with support for high-definition content playback and DirectX Video Acceleration.
The processor supports Advanced Configuration and Power Interface (ACPI) C-states, Enhanced Intel SpeedStep Technology, and various power management capabilities for system, memory controller, PCI Express, and Direct Media Interface.
Features include a Digital Thermal Sensor, Intel Adaptive Thermal Monitor, and support for thermal throttling and fan speed control.
The processor is housed in a 37.5 x 37.5 mm Flip Chip Land Grid Array (FCLGA 1155) package.
The document provides definitions for various terms and technologies related to the processor, such as ACPI, DDR3, DMI, Intel Virtualization Technology, and more.
The processor core refers to the silicon die containing multiple execution cores, each with its own instruction cache, data cache, and 256-KB L2 cache. All cores share the L3 cache.
The Integrated Memory Controller (IMC) supports DDR3 protocols with two independent 64-bit channels, each accessing up to two DIMMs. It supports various DDR3 data transfer rates and module configurations, including unbuffered and ECC options. The IMC supports single-channel and dual-channel modes, with dual-channel offering symmetric and asymmetric zones for optimized performance.
The IMC supports specific DDR3 speed bins and command signal modes. It allows for Just-in-Time Command Scheduling, Command Overlap, and Out-of-Order Scheduling to enhance memory access efficiency. The processor includes additional Memory Type Range Registers (MTRRs) for supporting larger memory capacities.
The processor supports PCI Express architecture, maintaining compatibility with the PCI addressing model. It uses packets for communication, with a layered architecture comprising Transaction, Data Link, and Physical Layers. The interface supports Gen2 speeds, offering increased bandwidth per lane compared to Gen1.
Intel Fast Memory Access (FMA) technology includes enhancements like Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling to optimize memory bandwidth and reduce latency. Data scrambling is used to minimize di/dt impact on DDR3 data buses.
The document references additional resources for detailed specifications and guidelines related to Intel processors and chipsets.
The Transaction Layer is responsible for assembling and disassembling Transaction Layer Packets (TLPs) for communication of transactions like read and write. It also manages the flow control of TLPs.
This layer acts as an intermediary between the Transaction and Physical Layers, handling link management, error detection, and correction. It ensures the integrity of TLPs and requests retransmission if errors are detected.
The Physical Layer includes circuitry for interface operation and converts data from the Data Link Layer into a serialized format for transmission across the PCI Express Link.
PCI Express extends configuration space to 4096 bytes per device/function, divided into a PCI-compatible region and an extended PCI Express region. The Host Bridge translates memory-mapped configuration space accesses.
The processor's PCI Express interface is a 16-lane port compliant with PCI Express Base Specification, Revision 2.0.
DMI connects the processor and PCH, supporting only DMI x4 configuration. It generates SERR in response to errors and is compatible with Intel 6 Series Chipset PCH.
The Graphics Engine Architecture includes 3D compute elements and a Multi-format decode/encode Pipeline for enhanced video quality and 3D performance.
The 3D engine supports up to 12 Execution Units and includes enhancements for video quality. The Video Engine supports VLD and MPEG2 decode in hardware.
The display is divided into Display Planes, Display Pipes, and Display Ports, supporting multiple independent display streams.
Intel FDI is a proprietary link for carrying display traffic, supporting two independent channels with a rate of 2.7 Gbps.
The processor supports simultaneous use of the Processor Graphics Controller and a x16 PCI Express Graphics device, allowing a maximum of 2 displays connected to each.
PECI is a one-wire interface for communication between a PECI client and master, allowing the communication of processor thermal and other information.
The document outlines the internal clocking requirements for processors, specifying a reference input clock frequency of 100 MHz for various interfaces including Processor, Memory, Graphics, PCIe, DMI, and FDI.
This section provides a high-level description of Intel technologies implemented in processors, with variations across different SKUs. Detailed information is available on Intel's technology website.
Intel VT allows a single system to appear as multiple independent systems, enabling multiple operating systems to run simultaneously. Key components include Intel VT-x for hardware support in processors and Intel VT-d for I/O virtualization. Features of Intel VT-x include Extended Page Tables, Virtual Processor IDs, Guest Preemption Timer, and Descriptor-Table Exiting. Intel VT-d focuses on domain-based isolation and hardware-based virtualization, supporting features like DMA remap engines and interrupt remapping.
Intel TXT provides platform-level enhancements for creating trusted platforms, ensuring the authenticity and integrity of the controlling environment. It includes mechanisms for measured and verified launch of system software and protection against unauthorized modifications.
This technology allows an execution core to function as two logical processors, sharing some resources but maintaining separate architectural states. It requires BIOS and operating system support and is recommended for use with specific Windows operating systems.
Turbo Boost allows processor cores to run faster than their rated frequency when operating below power, temperature, and current limits. It dynamically adjusts frequency based on workload demand, optimizing performance for both processor and graphics.
Intel AVX extends the Intel SSE from 128-bit to 256-bit vectors, enhancing performance for applications requiring vector floating-point operations. It offers improved performance through wider vectors and new functionalities.
Intel AES-NI provides SIMD instructions for fast and secure data encryption and decryption based on AES, supporting a wide range of cryptographic applications.
The x2APIC architecture extends xAPIC for improved interrupt delivery and increased processor addressability, offering backward compatibility and new features for enhanced performance.
- Processor Addressability: x2APIC mode increases the physical xAPIC ID field from 8 bits to 32 bits, allowing addressability up to 4G-1 processors. The logical xAPIC ID field also increases to 32 bits, partitioned into a 16-bit cluster ID and a 16-bit logical ID within the cluster.
- MSR Interface: APIC registers are accessed through Model Specific Register (MSR) interfaces, enhancing interrupt delivery and virtualization capabilities.
- Software Compatibility: x2APIC provides backward compatibility with xAPIC and requires a new OS and BIOS for full functionality.
- ACPI States: The processor supports various ACPI states, including G0 (Working), G1 (Sleeping), G2 (Soft Off), and G3 (Mechanical Off).
- Processor Core States: Includes C0 (Active), C1 (Auto Halt), C1E (Auto Halt with low frequency/voltage), C3 (Cache flush, clocks off), C6 (Save core states), and C7 (Similar to C6 with L3 flush).
- Integrated Memory Controller States: Power up, Pre-charge Power-down, Active Power-Down, and Self-Refresh states are supported.
- PCI Express and DMI States: Includes L0 (Active), L0s (Low power), L1 (Lowest power), and L3 (Power-off).
- Frequency and Voltage Optimization: Multiple P-states for optimal performance and power efficiency, controlled via software.
- Voltage Ramp Rates: Controlled internally for glitch-free transitions, allowing numerous transitions per second.
- C-States: Higher C-states save more power but have longer latencies. C-state auto-demotion optimizes power usage by demoting C6 to C3 or C1 based on residency history.
- Package C-States: Determined by the lowest core C-state, allowing for additional power savings depending on platform components.
The document outlines various power management states and techniques for processors, focusing on package C-states, integrated memory controller (IMC) power management, PCI Express, Direct Media Interface (DMI), and graphics power management.
- Package C0: Normal operating state where at least one core is active.
- Package C1/C1E: No additional power reduction in C1, but C1E reduces core clock frequency and voltage.
- Package C3: Entered when at least one core is in C3 state; L3 cache remains valid.
- Package C6: Entered when cores are in C6 state; core voltages are reduced to zero, but L3 cache remains powered.
- Disabling Unused Memory Outputs: Reduces power by tri-stating unused signals.
- DRAM Power Management: Utilizes CKE signals for power-saving modes like Active Power-Down (APD), Precharged Power-Down (PPD), and DLL-off.
- Conditional Self-Refresh: Memory enters self-refresh in low-power states like C3 and C6.
- Dynamic Power-down: Aggressively manages power-down based on idle conditions.
Supports active power management using L0s and L1 states, with inputs and outputs disabled in L2/L3 Ready state.
- Intel Rapid Memory Power Management (RMPM): Puts memory into self-refresh during C3/C6 states.
- Intel Graphics Performance Modulation Technology (GPMT): Dynamically adjusts render frequency and voltage.
- Render C-State (RC6): Optimizes power during idle times by reducing voltage.
- Intel Smart 2D Display Technology (S2DDT): Reduces memory traffic for display refresh, effective in static screens.
- Intel Graphics Dynamic Frequency: Increases frequency and voltage based on power and thermal budget.
For detailed thermal specifications and design guidelines, refer to specific Intel processor family documentation.
This section outlines various signal types and their buffer characteristics. Key signals include PCI Express, Direct Media Interface (DMI), CMOS, DDR3, and Analog signals. Each signal type has specific voltage tolerances and coupling methods, such as AC or DC coupling for PCI Express and DMI signals.
Memory Channel A and B signals are detailed, including Bank Select, Write Enable, RAS, CAS, Data Strobes, Data Bus, Memory Address, and Clock signals. These signals are crucial for SDRAM operations and are primarily DDR3 buffer types.
This section describes configuration signals, power management sync, platform reset, and reserved signals. It includes PCI Express bifurcation options and the role of signals like PM_SYNC and RESET#.
Details on PCI Express graphics interface signals, including current and resistance compensation, and differential pairs for transmit and receive operations.
Describes the DMI signals used for processor to PCH serial interface, including differential pairs for input and output.
Includes signals for differential bus clock input and various test and debug signals like TCK, TDI, TDO, and TRST#.
Signals like CATERR#, PECI, PROCHOT#, and THERMTRIP# are used for error signaling and thermal protection, indicating system errors and processor temperature status.
Describes signals related to power sequencing and processor power supply, including VCC, VCCIO, VDDQ, and others. It also covers the serial VID interface for power management.
Details on sense signals for voltage measurement and ground signals for processor stability.
Lists signals with internal pull-up or pull-down resistors, specifying their resistance values and associated power rails.
Discusses power and ground lands, emphasizing the importance of connecting power lands to processor power planes and using multiple planes to reduce I*R drop. It also introduces the serial VID interface for voltage determination.
The document emphasizes the importance of designing the board to ensure that the voltage provided to the processor remains within specified limits to avoid timing violations or reduced processor lifespan. It highlights the need for bulk capacitance with low effective series resistance (ESR) and low interconnect resistance from the regulator to the socket. Proper bulk decoupling is necessary to handle large current swings during power-on or transitions between power states.
The processor uses a differential clock to generate various internal frequencies. The core frequency is determined by multiplying the core ratio by the BCLK frequency. An internal phase-locked loop (PLL) is used for clock multiplication, requiring a constant frequency input, except for Spread Spectrum Clocking (SSC). The maximum non-turbo core frequency is set during power-on reset, with options to configure lower speeds using the FLEX_RATIO MSR.
An on-die PLL filter solution is implemented, with DC specifications provided in Table 7-6.
The processor uses a serial voltage identification interface to support automatic voltage selection. The VID values, which can change due to temperature or current load changes, are specified in Table 7-1. The document notes that individual processor VID values may vary, allowing operation while transitioning to an adjacent VID and its associated voltage.
The VCCSA is configured by the processor output pin VCCSA_VID, with default logic state low for processors. Table 7-2 specifies different VCCSA_VID configurations.
The document provides guidelines for handling reserved signals, emphasizing that arbitrary connections may result in malfunction or incompatibility. Unused inputs should be connected to an appropriate signal level, and unused outputs may be left unconnected.
Signals are grouped by buffer type and characteristics, with details provided in Table 7-3. The document specifies requirements for Control Sideband Asynchronous signals and provides guidelines for Test Access Port (TAP) connections.
The document supports IEEE 1149.1-2001 and IEEE 1149.6-2003 standards for boundary scan (JTAG), with some I/O pins supporting only one of these standards.
Various sensing points are mentioned, including VCC_SENSE, VSS_SENSE, VCCIO_SENSE, and others, which are critical for monitoring voltage and current levels.
The document details differential input and output signals for PCI Express and DMI, indicating the processor's capability to handle high-speed data transfer.
The document specifies storage conditions, including absolute maximum and minimum storage temperatures (-25°C to 125°C) and sustained storage conditions (-5°C to 40°C, 60% humidity at 24°C) to ensure long-term reliability.
Detailed DC voltage and current specifications are provided for processor core, system agent, and graphics, with specific parameters for different processor models (e.g., 95W, 65W, 45W, and 35W TDPs).
The document outlines DC specifications for DDR3 signals, including input/output voltage levels and buffer resistances, ensuring compatibility and performance.
Specifications for control sideband and TAP signals are provided, including input/output voltage levels and buffer resistance, crucial for signal integrity.
The document includes specifications for PCI Express DC parameters, such as differential peak-to-peak voltage swing and common mode output voltage, essential for maintaining signal quality.
The document outlines various electrical specifications for DC differential and common mode impedances, peak-to-peak voltages, and resistance values. Key parameters include DC Differential Tx Impedance (80-120 Ω), DC Common Mode Rx Impedance (40-60 Ω), and Differential Rx input Peak to Peak Voltage for Gen1 (0.175-1.2 V) and Gen2 (0.12-1.2 V).
PECI is an Intel proprietary interface for communication between processors and external thermal monitoring devices. It uses a Digital Thermal Sensor (DTS) to report die temperature. The PECI bus architecture is based on a wired OR bus, with idle state near zero. The interface operates at a nominal voltage set by VCCIO, with specific DC electrical limits provided.
The document includes detailed processor pin assignments and signal information, with pin maps for different quadrants of the socket. It lists processor pins alphabetically by pin name, detailing buffer types and directions for each pin.
This section provides a detailed list of processor pins, specifically focusing on the VSS (ground) pins. Each pin is listed with its corresponding pin number, indicating its connection to the ground (GND). This information is crucial for understanding the grounding scheme of the processor.
The document discusses DDR Data Swizzling, a technique used to enhance memory performance and timing. Swizzling rearranges the data pins to optimize the use of the product across various platforms. It is noted that swizzling does not affect the functional operation and remains invisible to the operating system and software. However, it is important during debugging, as engineers must consider the swizzling table for effective memory analysis.
The document includes detailed tables for DDR Data Swizzling for Channels A and B. Each table maps the SA_DQ and SB_DQ pin names to their respective MC (Memory Controller) pin names. This mapping is essential for engineers to understand the physical layout and logical connections of the DDR data pins, facilitating efficient debugging and performance optimization.
Catalog excerpts
2nd Generation Intel® Core™ Processor Family Desktop, Intel® Pentium® Processor Family Desktop, and Intel® Celeron® Processor Family Desktop Datasheet, Volume 1 Supporting Intel® Core™ i7, i5, and i3 Desktop Processor Series Supporting Intel® Pentium® Processor G800 and G600 Series Supporting Intel® Celeron® Processor G500 and G400 Series This is Volume 1 of 2
Open the catalog to page 1
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Legal Lines...
Open the catalog to page 2
Revision History Revision Number 001 Revision Date Initial release • Added Intel® Core™ i5-2405S, i5-2310, and i3-2105 processors 002 • Added Intel® Pentium® processor family desktop – Intel® Pentium® G850, G840, G620, and G620T processors • Added Intel® Core™ i5-2320, i3-2125, i3-2130, and i3-2120T processors 003 • Added Intel® Celeron® processor family desktop – Intel® Celeron G540, G530, G530T, and G440 processors • Added Intel® Pentium® G860, G630, and G630T processors October 2011 • Added Intel® Core™ i7-2700K processor • Added Intel® Celeron® G460 processor • Added Intel® Core™ i5-2550K,...
Open the catalog to page 8
Introduction The 2nd Generation Intel® Core™ processor family desktop, Intel® Pentium® processor family desktop, and Intel® Celeron® processor family desktop are the next generation of 64-bit, multi-core desktop processor built on 32- nanometer process technology. Based on a new micro-architecture, the processor is designed for a two-chip platform consisting of a processor and Platform Controller Hub (PCH). The platform enables higher performance, lower cost, easier validation, and improved x-y footprint. The processor includes Integrated Display Engine, Processor Graphics, PCI Express* ports,...
Open the catalog to page 9
Desktop Platform System Block Diagram Example PCI Express* 2.0 1 x16 or 2x8 Discrete Graphics (PEG) Processor PECI Intel® Flexible Display Interface Intel® Management Engine LVDS Flat Panel WiFi / WiMax Gigabit Network Connection
Open the catalog to page 10
Processor Feature Details • Four or two execution cores • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction/data second-level cache (L2) for each core • Up to 8-MB shared instruction/data third-level cache (L3), shared among all cores Supported Technologies • Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) • Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) • Intel® Active Management Technology 7.0 (Intel® AMT 7.0) • Intel® Trusted Execution Technology (Intel®...
Open the catalog to page 11
• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank devices) • Command launch modes of 1n/2n • On-Die Termination (ODT) • Asynchronous ODT • Intel® Fast Memory Access (Intel® FMA) — Just-in-Time Command Scheduling — Command Overlap — Out-of-Order Scheduling PCI Express* • PCI Express* port(s) are fully-compliant with the PCI Express Base Specification, Revision 2.0. • Processor with desktop PCH supported configurations PCI Express* Supported Configurations in Desktop Products Configuration • The port may negotiate down to narrower widths — Support for x16/x8/x4/x1 widths...
Open the catalog to page 12
• 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros) • 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped. • Re-issues Configuration cycles that have been previously completed with the Configuration Retry status • PCI Express* reference clock is 100-MHz differential clock • Power Management Event (PME) functions...
Open the catalog to page 13
Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between a PECI client (the processor) and a PECI master. The processors support the PECI 3.0 Specification. Processor Graphics • The Processor Graphics contains a refresh of the sixth generation graphics core enabling substantial gains in performance and lower power consumption. • Next Generation Intel Clear Video Technology HD support is a collection of video playback and enhancement features that improve the end user’s viewing experience. — Encode/transcode HD content — Playback...
Open the catalog to page 14
Power Management Support Processor Core • Full support of Advanced Configuration and Power Interface (ACPI) C-states as implemented by the following processor C-states — C0, C1, C1E, C3, C6 • Enhanced Intel SpeedStep® Technology Memory Controller • Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM)) • Dynamic power-down PCI Express* • L0s and L1 ASPM power management capability Direct Media Interface (DMI) • L0s and L1 ASPM power management capability Processor Graphics Controller • Intel® Rapid Memory Power Management (Intel® RMPM) – CxSR • Intel® Graphics Performance...
Open the catalog to page 15
Package • The processor socket type is noted as LGA 1155. The package is a 37.5 x 37.5 mm Flip Chip Land Grid Array (FCLGA 1155). See the 2nd Generation Intel® Core™ Processor, Intel® Pentium® Processor, and Intel® Celeron® Processor, and LGA1155 Socket Thermal Mechanical Specifications and Design Guidelines for complete details on package. Terminology (Sheet 1 of 2) Term Advanced Configuration and Power Interface Block Level Transfer Third-generation Double Data Rate SDRAM memory technology Direct Memory Access Direct Media Interface Digital Thermal Sensor Enhanced Intel SpeedStep® Technology...
Open the catalog to page 16All Intel catalogs and technical brochures
10th Gen Intel® Core7 Pages
10th Gen8 Pages
nuc-celeron4 Pages
Intel® NUC 8 Home Mini PC4 Pages
Intel® Xeon® Scalable Platform14 Pages
Intel® Ethernet Controller XL7101726 Pages
Intel® Xeon® Processor E3-1200 v5130 Pages
Intel® Quark™ SoC X1000 Series934 Pages
Intel® X99 Chipset4 Pages
Intel® Desktop Board DQ67EP4 Pages
Intel® Ethernet Switch FM4000270 Pages
Intel® NUC Board DE3815TYBE82 Pages
S2600GZ and S2600GL245 Pages
i7-lga2011314 Pages
c600-series936 Pages
b75-express4 Pages
desktop-board4 Pages
3rd-gen-core-desktops2 Pages
/3rd-gen-core2 Pages
Archived catalogs
Intel® Ethernet Controllers2 Pages
Intel® 3450 Chipset2 Pages
Intel® 3000 and 3010 Chipset4 Pages
Intel® X58 Express Chipset4 Pages
Intel® Server Board S1200BT8 Pages
Intel® Desktop Board DX58SO24 Pages
- Management software solution
- Analysis software solution
- Real-time software
- Computer-aided design software
- Cloud-based software
- Design software solution
- Monitoring software solution
- Interface software
- Visualization software solution
- Simulation software solution
- Programming software
- Development software
- Network software
- Creation software
- Test software
- Optimization software
- Wireless module
- Solid-state drive
- Internal solid-state drive
- High-performance software