DDR3L SDRAM Device Operation
147Pages

DDR3L SDRAM Device Operation

Contents 1. Functional Description 1.1 Simplified State Diagram 1.2 Basic Functionality 1.3 RESET and Initialization Procedure 1.3.1 Power-up Initialization Sequence 1.3.2 Reset Initialization with Stable Power 1.4 Register Definition 1.4.1 Programming the Mode Registers 1.4.2 Mode Register MR0 1.4.3 Mode Register MR1 1.4.4 Mode Register MR2 1.4.5 Mode Register MR3 2. DDR3 DRAM Command Description and Operation 2.1 Command Truth Table 2.2 CKE Truth Table 2.3 No Operation (NOP) Command 2.4 Deselect Command 2.5 DLL-off Mode 2.6 DLL on/off switching procedure 2.6.1 DLL “on” to DLL “off”...

DDR3L Device Operation 2.14.5 tWPST Calculation 2.15 Refresh Command 2.16 Self-Refresh Operation 2.17 Power-Down Modes 2.17.1 Power-Down Entry and Exit 2.17.2 Power-Down clarifications - Case 1 2.17.3 Power-Down clarifications - Case 2 2.17.4 Power-Down clarifications - Case 3 3. On-Die Termination (ODT) 3.1 ODT Mode Register and ODT Truth Table 3.2 Synchronous ODT Mode 3.2.1 ODT Latency and Posted ODT 3.2.2 Timing Parameters 3.2.3 ODT during Reads 3.3 Dynamic ODT 3.3.1 Functional Description 3.3.2 ODT Timing Diagrams 3.4 Asynchronous ODT Mode 3.4.1 Synchronous to Asynchronous ODT Mode...

DDR3L Device Operation 5.7 Output Driver DC Electrical Characteristics 5.7.1 Output Driver Temperature and Voltage sensitivity 5.8 On-Die Termination (ODT) Levels and I-V Characteristics 5.8.1 On-Die Termination (ODT) Levels and I-V Characteristics 5.8.2 ODT DC Electrical Characteristics 5.8.3 ODT Temperature and Voltage sensitivity 5.9 ODT Timing Definitions 5.9.1 Test Load for ODT Timings 5.9.2 ODT Timing Definitions 6. Electrical Characteristics & AC Timing for DDR3L-800 to DDR3L-1866 6.1 Clock Specification 6.1.1 Definition for tCK (avg) 6.1.2 Definition for tCK (abs) 6.1.3 Definition...

1. Functional Description 1.1 Simplified State Diagram This Simplified State Diagram is intended to provide an overview of the possible state transitions and the commands to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die termination, and some other events are not captured in full detail. Power applied Reset Procedure Active Power Down Precharge Power Down Bank Active WRITE Automatic Sequence Command Sequence Figure 1. Simplified State Diagram Table 1: State Diagram Command Definitions Abbreviation Active Precharge Precharge All Mode...

 The DDR3 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM. The DDR3 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR3 SDRAM are burst...

1.3 RESET and Initialization Procedure 1.3.1 Power-up Initialization Sequence  The following sequence is required for POWER UP and Initialization. 1. Apply power (RESET# is recommended to be maintained below 0.2 x VDD; all other inputs may be undefined). RESET# needs to be maintained for minimum 200 us with stable power. CKE is pulled “Low” anytime before RESET# being de-asserted (min. time 10 ns). The power voltage ramp time between 300 mv to VDDmin must be no greater than 200 ms; and during the ramp, VDD > VDDQ and (VDD - VDDQ) < 0.3 volts. • VDD and VDDQ are driven from a single power...

tDLLK tMRD tIS (( (( (( (( )) )) )) )) Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or( LOW ( (( (( (( )) )) )) )) NOTE 1. From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands. TIME BREAK DON’T CARE Figure 2. Reset and Initialization Sequence at Power-on R

DDR3L Device Operation 1.3.2 Reset Initialization with Stable Power  The following sequence is required for RESET at no power interruption initialization. 1. Asserted RESET below 0.2 * VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to be maintained for minimum 100 ns. CKE is pulled “LOW” before RESET being deasserted (min. time 10 ns). 2. Follow Power-up Initialization Sequence steps 2 to 11. 3. The Reset sequence is now completed; DDR3 SDRAM is ready for normal operation. Tb tDLLK tMRD tIS (( (( (( (( )) )) )) )) Static LOW in case RTT_Nom is enabled at...

1.4 Register Definition 1.4.1 Programming the Mode Registers  For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. As the default values of the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized and/or re-initialized, i.e., written, after power up and/or reset for proper operation. Also the contents of the Mode Registers can be altered by re-executing the MRS command during...

DDR3L Device Operation The mode register contents can be changed using the same command and timing requirements during normal operation as long as the DRAM is in idle state, i.e., all banks are in the precharged state with tRP satisfied, all data bursts are completed and CKE is high prior to writing into the mode register. If the RTT_NOM Feature is enabled in the Mode Register prior and/or after an MRS Command, the ODT Signal must continuously be registered LOW ensuring RTT is in an off State prior to the MRS command. The ODT Signal may be registered high after tMOD has expired. If the...

1.4.2 Mode Register MR0 The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge PowerDown, which include various vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting low on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2, while controlling the states of address pins according to Figure 6. Address Field *1: BA2 and A13~A15 are RFU and must be programmed to 0 during MRS. *2: WR (write...