TDI-CCD image sensors S14810 Hybrid structure combining TDI-CCD and CMOS readout circuit These image sensors combine a TDI-CCD, which can ensure adequate brightness for images even during high speed imaging, with a CMOS readout circuit for digital output. The S14813 (back-thinned type) has higher sensitivity than the S14810 (frontilluminated type) in the ultraviolet to visible region, ensuring clear images even at low illuminance. Sensors combining TDI-CCD and CMOS readout circuit Continuous imaging of high-speed moving objects Effective bit number: 9.4-bit (data width: 10-bit) Machine vision High-speed line rate: 100 kHz max. High UV resistance (S14813) Low noise: 12 e- rms typ. (S14813) 8 e- rms typ. (S14810) Bidirectional transfer Structure Parameter Pixel size (H × V) Total number of pixels (H × V) Number of effective pixels (H × V) Image size (H × V) Fill factor Number of TDI stages Anti-blooming Vertical clock Output circuit Package S14810 Window material S14813 Cooling Specification 12 × 12 μm 1024 × 132 1024 × 128 12.288 × 1.536 mm 100% 128 FW × 100 min. 2-phase (bidirectional) 10-bit A/D converter 320-pin ceramic (see dimensional outlines) Borosilicate glass*1 Quartz glass*1 Non-cooled *1: Resin sealing Note: This product is not hermetically sealed, and therefore moisture may penetrate into the package. Storing or using the product in a place with sudden temperature or humidity changes may cause condensation to form inside the package, so avoid such environments.

TDI-CCD image sensors Absolute maximum ratings (Ta=25 °C unless otherwise noted) Parameter Operating temperature*2 Storage temperature Output transistor drain voltage Reset drain voltage Overflow drain voltage Overflow gate voltage Summing gate voltage Reset gate voltage Output gate voltage Vertical clock voltage CCD ground voltage Analog terminal ROIC supply voltage Digital terminal Counter terminal ROIC digital input terminal voltage*3 Soldering conditions*4 Symbol Topr Tstr VOD VRD VOFD VOFG VSG VRG VOG VPXV VAGND Vdd(A) Vdd(D) Vdd(C) Vi Tsol *2: Package temperature *3: SPI_CS, SPI_SCLK, SPI_MOSI,...

TDI-CCD image sensors Electrical characteristics Digital input [Ta=25 °C, Typ. values in operating conditions table (P.2), unless otherwise noted] Parameter Master clock pulse frequency Master clock pulse duty ratio Rise time*6 *7 Digital input signal Fall time*6 *7 Symbol f(CLK) D(CLK) tr(sigi) tf(sigi) *6: SPI_CS, SPI_SCLK, SPI_MOSI, SPI_RSTB, CLK, TG_reset, PLL_reset *7: Time for the input voltage to rise or fall between 10% and 90% Digital output [Ta=25 °C, Typ. values in operating conditions table (P.2), unless otherwise noted] Parameter Data rate Pixel sync signal (PCLK) frequency Offset...

TDI-CCD image sensors Electrical and optical characteristics [Ta=25 °C, Typ. values in operating conditions table (P.2), unless otherwise noted] Parameter Spectral response range Conversion efficiency Saturation output*16 Full well capacity*17 Vsat FW Vsat PRNU DS DSD Nread RN Drange Vo DSNU Unit nm μV/eDN/eμV/eDN/eDN keV % ke-/pixel/s DN/s e- rms DN rms DN DN rms Gain=1x Gain=10x Maximum output, where linearity is ±5% or smaller while the offset output is subtracted Electron charge corresponding to saturation output PRNU=∆X/X × 100 [%] ∆X: standard deviation of all effective pixel output, X:...

TDI-CCD image sensors Spectral response (with window) (Typ. Ta=25 °C) Quantum efficiency (%) Spectral transmittance of window material Dark current vs. chip temperature Dark current (ke-/pixel/s)

TDI-CCD image sensors Sensor structure

TDI-CCD image sensors Block diagram CLK, TG_reset PLL_reset SPI_SCLK_b, SPI_RSTB_b SPI_CS_b, SPI_MOSI_b 24 Horizontal shift register Timing generator Column parallel A/D converter LVDS output Vsync_b Hsync_b CTR_b PCLK_b Bias circuit Column amplifier Column amplifier Column parallel A/D converter Horizontal shift register Timing generator LVDS output Bias circuit Vsync_a Hsync_a CTR_a PCLK_a SPI_SCLK_a, SPI_RSTB_a SPI_CS_a, SPI_MOSI_a KMPDC0792EA

TDI-CCD image sensors Timing chart PCLK Vsync Hsync CTR Out_A[0] 1st pixel data 2nd pixel data 3rd pixel data Invalid data Vsync Hsync Invalid data Valid data Invalid data Valid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Valid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Valid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Valid data Invalid data Valid data Invalid data 1st line data (256 pixels) 2nd line data (256 pixels) KMPDC0793EB

TDI-CCD image sensors TDI mode tpwvs Output Vsync tpwhs Vref_x (open) Vertical clock phase Readout port A B RG, SG, Vref Readout port A B ADC_N [7:0], DO_N [7:0] Readout port A B

TDI-CCD image sensors Area scanning mode Integration period (shutter open) Output Transfer period (shutter closed) Vsync tpwhs Vref_x (open) Vertical clock phase Readout port A B RG, SG, Vref Readout port A B ADC_N [7:0], DO_N [7:0] Readout port A B Parameter Pulse width PXV, PYV*24 Rise and fall times SG*24 Duty ratio Pulse width RG Rise and fall times Vsync-CCD clock timing shift Symbol tpwv tprv, tpfv tpwr tprr, tpfr tts *24: Symmetrical clock pulses should be overlapped at 50% of maximum pulse amplitude.

TDI-CCD image sensors Vsync Hsync Parameter Pulse width*25 Pulse width*25 Symbol tpwvs tpwhs Unit cycles cycles *25: One cycle is the period of a single master clock cycle. Digital output timing Reset input at power-on Raise all the supply voltage to meet the operating conditions, then input “Tg_reset” and “SPI_RSTB” as shown below to initialize the timing generator and the SPI circuit. Vdd(A) Vdd(D) MCLK tr(psv) tPW(Reset) tPW(RSTB) [Ta=25 °C, Typ. values in operating conditions in table (P.2), unless otherwise noted] Parameter SPI_RSTB signal low period at power-on Interval between SPI_RSTB...

TDI-CCD image sensors Digital output (LVDS) PCLK Vsync tPDVF Hsync tPDHF Vdiff tPDD tr(out) tf(out) Parameter Data rate (per port) Digital output voltage Offset (LVDS output) Differential Rise time*29 *30 Digital output signal Fall time*29 *30 PCLK - Dout delay time Rise time PCLK - Hsync delay time Fall time Rise time PCLK - Vsync delay time Fall time Rise time PCLK - CTR delay time Fall time Symbol VR Vofs Vdiff tr(out) tf(out) tPDD tPDHR tPDHF tPDVR tPDVF tPDCR tPDCF *29: Dout, Vsync, Hsync, PCLK, CTR *30: Time for the output voltage to rise or fall between 10% and 90% when there is a 10 pF...