CCD image sensors S14651/S14661 series Photosensitive area structure suitable for spectrometers, high-speed/low-noise type available (1-stage TE-cooled) The S14651/S14661 series are back-thinned CCD image sensors designed for spectrometers. Low-noise type (S14651 series) and high-speed type (S14661 series) are available. The S14650/S14660 series offer nearly flat spectral response characteristics with high quantum efficiency from the UV to near infrared region. A thermoelectric cooler is placed inside the package to keep the chip temperature constant (approx. 5 °C) during operation. One-stage TE-cooled type (chip temperature: approx. 5 °C) Low etaloning High sensitivity over a wide spectral range and nearly flat spectral response characteristics High conversion efficiency: 6.5 μV/e- (S14651 series) 8 μV/e- (S14661 series) High full well capacity and wide dynamic range (Horizontal shift register with anti-blooming function) Pixel size: 14 × 14 μm Selection guide Type no. Total number of pixels Number of effective pixels Suitable driver circuit Structure Parameter Pixel size (H × V) Vertical clock Horizontal clock Output circuit Package Window material*1 Cooling *1: Hermetically sealed One-stage MOSFET source follower Two-stage MOSFET source follower 28-pin ceramic DIP (refer to dimensional outlines) Quartz glass*1 One-stage TE-coole

Absolute maximum ratings (Ta=25 °C) Parameter Operating temperature*2 Storage temperature Output transistor S14651 series drain voltage S14661 series Reset drain voltage Output amplifier return voltage Overflow drain voltage Vertical input source voltage Horizontal input source voltage Overflow gate voltage Vertical input gate voltage Horizontal input gate voltage Summing gate voltage Output gate voltage Reset gate voltage Transfer gate voltage Vertical shift register clock voltage Maximum current of built-in TE-cooler*3 *4 Maximum voltage of built-in TE-cooler Horizontal shift register clock voltage...

Electrical characteristics [Ta=25 °C, operating conditions: Typ. value (P.2)] Parameter frequency*9 Output signal Vertical shift register capacitance -1024 -2048 Horizontal shift register -1024 capacitance -2048 Summing gate capacitance Reset gate capacitance -1024 Transfer gate capacitance -2048 Charge transfer efficiency*10 DC output level**9 Output impedance*9 Power consumption*9 *11 *9: The values depend on the load resistance (S14651 series: VOD=24 V, RL=100 kΩ, S14661 series: VOD=15 V, RL=2.2 kΩ) *10: Charge transfer efficiency per pixel, measured at half of the full well capacity *11: Power...

Spectral response (without window)*17 (Typ. Ta=25 °C) Quantum efficiency (%) *17: Spectral response will degrade depending on the transmittance characteristics of the quartz glass. Spectral transmittance characteristics of window material Dark current vs. temperature Dark current (e-/pixel/s)

Device structure (schematic of CCD chip as viewed from top of dimensional outline) S14651 series Effective pixels Thinning Effective pixels Horizontal shift register 4 blank pixels Horizontal shift register Note: When viewed from the light input side, the horizontal shift register is covered by the thick area of the silicon (insensitive area), but long-wavelength light may pass through the insensitive silicon area. This light may be received by the horizontal shift register. Take measures such as shielding the light. KMPDC0703EA S14661 series Effective pixels Thinning Effective pixels Horizontal...

Timing chart (line binning) Integration time (external shutter has to be open)* Vertical binning period (external shutter has to be closed)* Readout period (external shutter has to be closed)* P2V, TG Tpwh, Tpws Tovrh 1 * An external shutter is not necessarily required. When not using an external shutter, light entering during the vertical binning period and readout period is read out as signal. KMPDC0686EA Parameter P1V, P2V, Pulse width*18 TG Rise and fall times*18 Pulse width*18 P1H, P2H, Rise and fall times*18 P3H, P4H Pulse overlap time Duty ratio*18 Pulse width*18 Rise and fall times*18...

Dimensional outline (unit: mm) 48.0 45.5 38.0 Light input window 35.0 33.02 Index mark Photosensitive area Tolerance unless otherwise noted: ±0.15 Glass thickness (refractive index 1.5) Weight: 9 g * Distance from package bottom to photosensitive area Type no. S14651/ -1024 S14661 -2048 series

Function Output transistor source Output transistor drain Output gate Summing gate Substrate Reset drain Thermistor TE-coolerCCD horizontal register clock-4 CCD horizontal register clock-3 CCD horizontal register clock-2 CCD horizontal register clock-1 Remark (standard operation) RL=100 kΩ +24 V +5 V Same pulse as P4H GND +12 V Test point (horizontal input gate) Overflow gate Overflow drain Test point (horizontal input source) Test point (vertical input source) Substrate Reset drain TE-cooler+ Thermistor Test point (vertical input gate) CCD vertical register clock-2 CCD vertical register clock-1...

OS output waveform example S14651 series (fc=250 kHz, RL=100 kΩ, VOD=+24 V) Reset Signal feed-through Reset feed-through DC level (Reset level) Signal DC level (Reset level) Signal level Signal level High-speed signal processing circuit example (using S14661-1024/-2048 and analog front-end IC) Connect to FPGA SDATA SCLK SLOAD AVDD AVSS CAPB CAPT VINB CML VING OFFSET VINR AVSS AVDD AD9826KRS

Specifications of built-in TE-cooler (Typ., vacuum condition) Parameter Internal resistance Maximum heat absorption*19 Symbol Condition Rint Ta=25 °C Qmax *19: This is a theoretical heat absorption level that offsets the temperature difference in the thermoelectric cooler when the maximum current is supplied to the unit. (Typ. Th=25 °C) Voltage vs. current CCD temperature vs. current Specifications of built-in temperature sensor A thermistor chip is built in the same package with a CCD chip, and the CCD chip temperature can be monitored with it. A relation between the thermistor resistance and...