High-End CPU for Test and Application • NXP® PowerPC® QorlQ® T1022, 1.2 GHz, 64-bit architecture, Double Precision Floating Point Unit, Ethernet, ECC-RAM • Xilinx® ArtiX®-7 FPGA (XC7A75T) for local • 62 I/Os at connector PMC-P4 configurable via FPGA as single ended (LVTTL) or Health Features and Fallback Flash • Local voltage and temperature monitoring • Fail save firmware update by means of fallback Flash • Over temperature protection Wide Range of Software Support • QNX®, VxWorks® and Linux® BSPs available • Example source code for the FPGA included in the BSPs • Universal boot loader: “Das U-Boot” • EtherCAT® Master available • Additional connector P6 with (e.g.) • CAN (with IRIG-B timestamp) via P4 • PMC only version, without connectors P5 and P6 The XMC-CPU/T10 is equipped with a PMC and an XMC interface. The NXP PowerPC QorIQ T1022 with 1.2 GHz features two 64-bit e5500 Power Architecture® processor cores with high-performance data path acceleration architecture (DPaA) and network peripheral interfaces. The local memory bus is 64 bits wide plus 8 bits ECC with an overall capacity of 512 Mbyte. 16 Mbyte SPI Flash for boot loader and 32 Kbit IC EEPROM for U-Boot environment offer non-volatile memory spaces. The XMC-CPU/T 10 features a second 16 Mbyte 'fallback' SPI Flash, used for system recovery if a system crash occurs during a firmware update. Alternatively it can be used for application software. FPGA for Local Applications The Xilinx Artix-7 FPGA is connected to the CPU by local bus for low latency data exchange. For high bandwidth data exchange the FPGA is additionally connected to the CPU via PCI Express®. 62 LVTTL-I/Os of the FPGA are routed to the PMC-P4 connector. XMC/PMC Interfaces The XMC interface comes with 4-lane PCIe® bus and is designed according to VITA™ 42.3. The PMC interface supports 32 bit / 66 MHz PCI bus according to PCI Local Bus Specification 3.0. Gigabit Ethernet The XMC-CPU/T 10 is equipped with two Gigabit Ethernet interfaces accessible at the front panel, which give an excellent base for EtherCAT® applications. The USB host port supports USB 2.0. Software Support The Flash memory carries the standard boot program “Das U-Boot” and enables the XMC-CPU/T10 to boot various operating systems from on-board Flash, network or USB. BSPs are available for QNX, Linux and VxWorks. The BSPs include an example source code for the FPGA. Programming of the FPGAs is done via XILINX Toolchain. The esd EtherCAT Master Stack is available for all supported operating systems. esd offers standard PIM modules for CAN signals. Furthermore a CAN IP-core (CAN esdACC) is available on request, implemented in a customized configuration (number of CAN nodes, routing FPGA ^ P4). Additional 73 LVTTL I/Os at connector P6 or 34 LVDS I/Os are available on request as well as a Serial ATA interface. Furthermore other CPU-types (T1014, T1042) are applicable, also an additional MRAM and other serial interfaces (RS-232) via P4. Up to 2x 128 MByte Flash is available on request. The XMC-CPU/T 10 can be produced without the connectors P5 and P6 if the space on the carrier is limited. All these options are available for customized series production in reasonable quantities. Please contact our sales team for detailed information. esd electronics gmbh Vahrenwalder Str. 207 30165 Hannover/ Germany

XMC-CPU/T10XMC/PMC 64-bit PowerPC® T1022 Processor Board with FPGAFPGA Artix-7 XC7A75T Temperature Sensors Technical Specifications: Cooling method Relative humidity Power supply voltage Microcontroller NXP PowerPC QorlQ T1022, 64-bit, 1.2 GHz, Double Precision Floating Point Unit Memory 512 Mbyte DDR3 RAM, 64 bits wide + 8 bit ECC, 32 Mbyte Flash for boot loader with health controller, 32 Kbit 2C EEPROM for U-Boot environment, 32 Kbit 2C EEPROM for Bootstrapping, _4 Kbit 2C EEPROM for SPD info DDR RAM Real-Time Clock RTC with Gold Cap, backup time min. 7 days Bus Interfaces XMC XMC according...