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Xilinx Virtex-6 FPGA Front End Processing Board - Model TIC-FEP-VPX3b

Xilinx Virtex-6 FPGA Front End Processing Board - Model TIC-FEP-VPX3b
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Xilinx Virtex-6 FPGA Front End Processing Board - Model TIC-FEP-VPX3b - 1

3U VPX Front End FPGA Processor Single Board Computer with Enhanced Graphics Description The TIC-FEP-VPX3b is a 3U VPX front end processing board based on the Xilinx Virtex®-6 FPGA. It offers very high performance with low power consumption. Designed for applications requiring very high computational power in a compact 3U form factor, the TIC-FEP-VPX3b board combines the flexibility of a Virtex®-6 FPGA with high bandwidth VPX serial interfaces. An FMC mezzanine site expands the capability of the board to connect ADC, DAC, general I/O, video, sFPDP, or additional FPGA based FMC modules. As part of our 3U VPX range, the TIC-FEP-VPX3b, along with our Intel® and Freescale SBCs and our XMC carriers for I/O boards, provides the ideal platform for radar, sonar, electronic warfare, and other digital signal processing applications. The Virtex®-6 FPGAs used on the TIC-FEP-VPX3b are built on a 40-nanometer (nm) process using third-generation Xilinx ASMBL architecture. Equipped with the Virtex®-6 SX315T (or XC6VLX195T), the TIC-FEP-VPX3b provides the high-performance logic, high-bandwidth I/O and powerful DSP resources required by the most compute-intensive applications. The DDR3 memory supports a significant data transfer rate of up to 8 GB/s. The DDRII plus SRAM supports a throughput of up to 1600MB/s. The Fabric Links of the VPX backplane are connected to the FPGA GTX transceivers, allowing a data rate up to 6.5 Gbps, depending on the type of interface: PCIe (GEN2), Aurora, etc. (SRIO is available with a specific IP address). It is also possible to take advantage of the embedded 10/100/1000 MAC blocks to provide four Ethernet ports on the backplane. The TIC-FEP-VPX3b is compliant with several Module Profiles of the VITA 65 standard. The Virtex®-6 FPGA interfaces with its Mirror flash (local bitstream storage) and an SPI flash (user parameters storage) through a Spartan®-6 FPGA (LX-45T). The TIC-FEP-VPX3b is a VPX 3U / 4HP 0.8” (1” by request) board compliant with 3U module definitions of the VITA 46.0 standard. The FMC site of the TIC-FEP-VPX3b is fully compliant with the FPGA Mezzanine Card standard (VITA 57.1), allowing installation of FMC modules provided by Elma, third-party, or developed by the customer. These mezzanine modules allow use of the latest / best suited high resolution A/D components for the application. Also, the FMC can be equipped with I/O connectors to route sixteen differential pairs from the FMC module directly to the P2 VPX connector: FPGA -2 speed grade. 5 Gbps for FPGA -1 speed grade. It is available in standard, rugged, and conduction-cooled grades. Applications and Related Products • Signal processing applications require FPGA’s in a wide range of intelligence, homeland security and defense systems including signal intelligence, electronic warfare, high definition video processing and radar applications. • Multiple front end processing FPGA’s in an array architecture: • Custom backplanes – need a custom backplane o Support application data flows involving multiple data streams that architecture for your system? are assigned to different FGPA resources. Radar antenna array • Embedded computing products – Single Board Computers applications for example may divide into regions which can be associated (SBCs), networking switches, storage with a sensor area to be processed by a specific Elma FEP card. • FPGA based configurable I/O Example Order Number: TIC-FEP-VPX3b The 3U VPX Front End FPGA processor • Rear transition modules (RTMs), extender and load boards • Mounting trays • Thermal simulation • Qualification support Elma Electronic Inc. • 510.656.3400 • sales@elma.com • www.elma.com

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Xilinx Virtex-6 FPGA Front End Processing Board - Model TIC-FEP-VPX3b - 2

3U VPX Front End FPGA Processor Single Board Computer with Enhanced Graphics Features Processor Unit • Xilinx Virtex®-6 XC6VSX315T (others as needed) • Two banks of DDR3-800: 40-bit wide, 1.25 GBytes each • DDRII plus SRAM: 18 bits wide / 9MB • Four Reference Clocks MBytes flash: o One NOR Flash eeprom (128 MBytes) • PICI μ-controller for System Management (per VITA 46.11) • Four LEDs • Four switches for on-board user configuration VPX Interfaces • Four 4-lane fabric ports (on P1) o Four GTX x4 channel (Fat Pipes A, B, C & D) Accessories • Engineering kit : JTAG ports for FPGA direct...

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Xilinx Virtex-6 FPGA Front End Processing Board - Model TIC-FEP-VPX3b - 3

3U VPX Front End FPGA Processor Single Board Computer with Enhanced Graphics Block Diagram Interfaces P1 connector - Four 4-lane Fabric ports • Four GTX x 4 (ports A,B,C,D) • Two GTPx4 (ports B & C) - Two 1-lane ports • Dual GTPx1 link usable as two 1000BASE-KX ports - One RS232 port on (Rx/Tx) - GPIOs - user defined P2 connector - General purpose I/O (on P2) • Sixteen differential pairs • Sixteen differential pairs (from FMC I/O connector) FMC connector - One GTPx4 link - 80 differential pairs - Four clocks (LVDS Diff) FMC modules • TIC-DAC-FMCa : Quad 16-bit 800 Msps DAC • TIC-ADC-FMCa :...

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