VEGA™ - CIS113
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• * * • • Bringing life ^ ^ w to technology Data Sheet VEGA - CIS113 Large Area and Buttable CMOS Image Sensor Pixel size is 16 pm square ■ Eight parallel analogue output ports Each port has both reset and signal levels; external subtraction can give CDS ■ Back-illuminated sensitivity and low readout noise Excellent image quality ■ An easy to drive image sensor for use in astronomy and science applications Serial buses for row and column addresses ■ Can be butted together on three sides Large focal plane arrays can be built ■ Delivered in robust transport and handling jig This sensor has a large image area, 30.72 mm x 73.73 mm, with 1920 x 4608 pixels at 16 pm square. It is read out through 8 parallel analogue output ports, normally in rolling shutter mode. Each port has both reference and signal level outputs for both external CDS subtraction and to improve common mode noise rejection. Row and column addresses are input on serial buses, with separate row addressing for each half of the device and separate column addressing for each group of 240 columns. In full frame mode the basic readout rate is 1.8 fps, but by only reading a selection of row and column addresses it is possible to read a large number of small "Regions Of Interest" (ROI) and achieve a frame rate up to 20 fps. This is particularly useful when monitoring images like star fields, where most of the area is black. This package has minimal dead space on 3 sides to allow close butting to form a mosaic array. Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein. e2v technologies (uk) limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU United Kingdom Holding Company: e2v technologies plc Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492 Contact e2v by e-mail: enquiries@e2v.com or visit www.e2v.com for global sales and operations centres. © e2v technologies (uk) limited 2016 A1A-787285 Version 1, December 2016

CIS113 Back-side illuminated CMOS sensor PERFORMANCE (ELECTRO-OPTICAL SPECIFICATION) Grade 1 device performance at -25 °C will be within the limits specified by "max" and "min" in Table 1 when operated at the recommended supply voltages and with the recommended read timing. Grade 5 devices may not meet these limits. Table 1: Electro-optical characteristics at -25 °C. 1) There are also 6 rows or columns of dummy pixels along each edge of the active array. These pixels cannot be read and so have no address. 2) Settling to 99 % of final change in signal voltage. Measured with IREAd = 40 and...

CIS113 Back-side illuminated CMOS sensor 7) Charge to voltage conversion factor (CVF) includes in-pixel source follower and whole path to output pin. 11) Dark signal non-uniformity (DSNU) is the standard deviation of the pixel by pixel dark current. DSNU excludes defective pixels. 8) Electronic rolling shutter (ERS) readout noise is measured with external subtraction to give Correlated Double Sampling (CDS) and at 2 MP/s nominal pixel rate on each of the eight channels. Ipix set to 80 µA. Dark current shot noise will add to this readout noise. Grade 5 devices may have up to 7.0 e− rms mean...

CIS113 Back-side illuminated CMOS sensor Maximum allowed defect levels are indicated in Table 2: Table 3: Definitions of types of defect. violet or infrared regions. For EUV, VUV and X-ray detection an uncoated device may be preferable. Back-Thinning A back-thinned image sensor (CMOS or CCD) is fabricated on the front surface of the silicon and then subsequently processed for illumination from the reverse side. This avoids loss of transmission due to front surface features (metal tracks in CMOS or the electrodes in CCD) and also removes most of the etalon effect caused by multiple...

CIS113 Back-side illuminated CMOS sensor Correlated Double Sampling (CDS) Each video output has two pins, an IMAGESIG[n] and an IMAGEREF[n]. The on-chip sampling will put the light-dependent level on IMAGESIG[n] following a transfer from the photodiode to the sense node. This will include the kTC noise from the reset of the sense node. The IMAGEREF[n] output will give the reset (black) level plus the same kTC noise. By means of a differential pre-amplifier it is possible to subtract the kTC noise and black level from the signal level to give low total noise. Using two reads will increase...

CIS113 Back-side illuminated CMOS sensor PIX_LOAD_BUF -fsl—1 PIX_SHR_L - ' to EIGHT INDEPENDENT COLUMN ADDRESSES iiiiliiiiiiiilJLL ytYYyyyyttyytyyy O o Li- rn HI — a£ co m LU CD CD Figure 3: More detailed floorplan of CIS113 (front side view). Only a few sample tracks for the control signals (rst[m]_l/r, rst_global[m]_l/r, sel[m]_l/r and tra[m]_l/r), are shown in the array area of Figure 3 to keep the diagram clear, while showing that they run horizontally across the array. Similarly only a few column outputs (col[n]) and the power and ground connections (VPIX, VREFR and ASUB) are...

CIS113 Back-side illuminated CMOS sensor section Global shutter under DEVICE OPERATION for further details. When not used as a reset these act as an anti-blooming charge dump on the photodiode. PIX_LOAD_BUF is used to set which sampling circuits will sample the pixel outputs and which will drive the output pins. See Odd-even sampling and Figure 6 to Figure 9 later in this section for further details. Row addresses are loaded serially by either set of left or right pin signals, ROW_LOAD_L, ROW_CLK_L and ROW_SER_IN_L or ROW_LOAD_R, ROW_CLK_R and ROW_SER_IN_R. See the section TIMING...