TELEDYNE e2VEverywhereyoulook™ EV12AD550 Dual 12bits 1.5GSps ADC Space Grade DATASHEET OVERVIEW EV12AD550 is a dual S-band capable 12bit ADC intended for space applications that is built using a true single core architecture providing high spectral purity. With a 3dB input bandwidth up to 4.3GHz it allows for direct digitization in S-band without frequency down-conversion. Synthetic Aperture Radar systems will also be able to operate this ADC with reduced dynamic range at frequencies beyond 5GHz without frequency down-conversion. This device includes a multiple ADC chained synchronization feature. This would help designing large array of synchronous ADC for example in active antenna array or MIMO systems. Multichannel applications will benefit from a cross-talk isolation between inputs in excess of 80dB and Noise Power Ratio performance of 50dB in the first Nyquist zone. This device comes in a hermetic flip chip CCGA323 package in Aluminum Nitride with improved thermal performance and is planned for QML-V and ESCC certification. APPLICATIONS ■ Earth observation SAR payload ■ Telecommunication satellite payload ■ Satellite data links ■ Satellite altimeter ■ Satellite TWTA compensation system ■ Satellite to satellite laser data links FEATURES Dual channel 12 bits 1.5GSps ADC ■ Single core architecture ADC per channel ■ Differential analog input voltage: 1Vppd ■ Full Power Input bandwidth (-3dB): 4.3GHz ■ Differential clock input ■ Power consumption: 2.3W / channel ■ Power supplies: Single Rail 3.4V or Dual rail 3.4V/2.5V ■ Low latency output interface: LVDS DEMUX 1:1 or 1:2 ■ Package: Hermetic CCGA323 21x21mm / 1mm pitch, Aluminum nitride material ■ SPI configuration with space protection control ■ Multiple ADC chained synchronization ■ Test mode: ramp, flash, PRBS ■ Control bit: parity, in-range, trigger ■ Clock input at 3GHz PERFORMANCE @ 1.5GSps 4.3GHz analog input bandwidth (-3dB) 50 dB NPR over 1st Nyquist 48 dB NPR over 2nd Nyquist 46 dB NPR over 3rd Nyquist 45 dB NPR over 4th Nyquist 74 dBFS SFDR at 100MHz, -1dBFS 72 dBFS SFDR at 1900MHz, -8dBFS 60 dBFS SFDR at 3730MHz, -12dBFS 49 dBFS SFDR at 5300MHz, -12dBFS Latency < 10ns Whilst Teledyne e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. Teledyne e2v accepts no liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein. Teledyne e2v Semiconductors SAS, Avenue de Rochepleine, BP 123, 38521 Saint Egreve Cedex France Telephone: +33 (0)476 58 30 00 Facsimile: +33 (0)4 76 58 34 80. Contact Teledyne e2v by e-mail:HOTLINE : [email protected] for technical purpose and [email protected] for commercial information. Visit www.teledyne-e2v.com for global sales and operations centres © Teledyne e2v Semiconductors SAS 2017 DS-1

Dual channel 12 bits 1.5GSps ADC1 Block Diagrams 1.1 DEMUX 1:1 SYNC/TRIGG 1.2 DEMUX 1:2 ADR Channel A data ready High port BDR Channel B data ready High port Document subject to disclaimer on page 1

Dual channel 12 bits 1.5GSps ADC The EV12AD550 is a dual 12 bit 1.5GSps ADC featuring low latency LVDS parallel output with a built-in selectable 1:2 or 1:1 DEMUX to compromise between power consumption and ease of interfacing. The two channels can operate in phase or in opposition, thus allowing synchronous or interleaved sampling. Each channel is composed of a true single core ADC sampling at up to 1.5GSps. Based on an innovative architecture without internal interleaving, it provides high spectral purity. It offers an analog input bandwidth of up to 4.3GHz with 2 selectable configurations...

Dual channel 12 bits 1.5GSps ADC 3 Specifications 3.1 Absolute maximum ratings Absolute maximum ratings are limiting and stressing values (referenced to GND = 0V), to be applied individually, while other parameters are within specified operating conditions. Exposure above those conditions may cause permament damage. Long exposure to maximum ratings may affect device reliability. Functional operation at any other conditions those indicated in the operational section may affect devices performances and reliability. Table 1: Absolute maximum ratings Document subject to disclaimer on page 1

Dual channel 12 bits 1.5GSps ADC3.2 Recommended conditions of use Table 3: Recommended conditions of use Only MIN and MAX values are guaranteed Document subject to disclaimer on page 1

Dual channel 12 bits 1.5GSps ADC 3.4 Electrical characteristics for supplies, inputs and outputs Unless otherwise specified: - Typical values are given for typical supplies in single-rail configuration (Refer to Table 18 in section DEMUX 1:1 or 1:2 for more information) at Tamb = +25°C. - Minimum and maximum values are given over corresponding temperature range for typical power supplies. - Values are given with SDA disabled and reduced swing mode - Sampling frequency (Fs ) at 1.5Gsps Table 6: Electrical characteristics for supplies, inputs and outputs Parameter Test level Symbol Min Value Unit...

Dual channel 12 bits 1.5GSps ADC Parameter Document subject to disclaimer on page 1

Dual channel 12 bits 1.5GSps ADC Parameter Notes: 1. Refer to Table 18 in section DEMUX 1:1 or 1:2 for more information on power supplies management 2. Enabling SDA increases power consumption by 80mW (23mA on VCCA) 3. The DC analog common mode voltage is provided by the CMIREF output of the ADC 4. See section Input common mode trimming for more information on the range available. 5. For optimal performance, in terms of VSWR, the input impedance must be 100Q ± 5% and the analog input impedance must be digitally trimmed to cope with process deviation. Refer to section Input impedance trimming...

Dual channel 12 bits 1.5GSps ADC 3.5 Converter characteristics Unless otherwise specified: - Typical values are given for typical supplies in dual-rail configuration (Refer to Table 18 in section DEMUX 1:1 or 1:2 for more information) at Tamb = +25°C. Both cores comply with the below specification when the OTP have been loaded. - Minimum and maximum values depend on the test level. - Values are specified at Fs = 1.5GSps. - Values are given with SDA disabled, reduced swing mode. Table 7: Static characteristics Document subject to disclaimer on page 1