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Chip Scale Review Reprint

Chip Scale Review Reprint
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ChipScale www.ChipScaleReview.com • Plasma Processing • Wafer-Level Packaging

A New Approach to Wafer-Level Packaging Employs Spin-On and Printable Silicones New material families that address today’s wafer-level processing needs include photo-patternable spin-on and printable silicones that offer thermal stability and minimize stress. Employed in suitable applications, they offer enhanced productivity in manufacturing. By Thorsten Meyer and Dr. Harry Hedler, Infineon Technologies, Dresden, Germany [infineon.com]; and Lyndon Larson and Michael Kunselman, Dow Corning, Midland, Mich. [dowcorning.com] he 2003 version of the International Technology Roadmap for...

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Figure 1. The redistribution layer is achieved by At some point, the holes become too small to print through or too dense to maintain stencil integrity, requiring the use of alternative processes. Cost-sensitive devices with moderateto-low density interconnect patterns, such as memory products, are viewed as ideal candidates for WLP, since the typical chip size and pincounts enable the use of standard, low-cost boards with pitches of 0.65mm and above. The transition to 300mm wafers more than doubles the number of chips per wafer, further reducing cost per die. New Materials printing holds a...

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less complex than the conventional contact by an array of pins. Low-Contact Resistivity Figure 2. This finite element model shows spiral metallization. the pads from the chip to the bumps is achieved by sputter and plate. The metal stack is applied after structuring a resist with photolithography. The metal stack is situated on top of the bump, making the electrical contact with the interconnect pads in test and assembly. Spiral RDL The plated metal is a Cu/Ni/Au stack, with a high conductivity due to the copper. In addition, because of the gold finish, The metal serves as a reliable...

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Component Level Test Shipping Simulation Pressure Cooker Test High Temperature Storage Temperature Cycling tivity in manufacturing, delivering excellent thermal, electrical and reliability performance along with the potential for the smallest form factors in packaging. These properties can be reached by using the new resilient contact element combined with a thin-film redistribution layer. Due to the simple process flow and full parallel processing, this technology is now available at low cost. The possibility of extending the backend flow from wafer-level test to a wafer-level test and...

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