CMOS Programmable Peripheral Interface The Harris 82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. The high performance and industry standard conguration of the 82C55A make it compatible with the 80C86, 80C88 and other microprocessors. Pin Compatible with NMOS 8255A 24 Programmable I/O Pins Fully TTL Compatible High Speed, No “Wait State” Operation with 5MHz and 8MHz 80C86 and 80C88 Direct Bit Set/Reset Capability Enhanced Control Word Read Capability L7 Process 2.5mA Drive Capability on All I/O Ports Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µA Static CMOS circuit design insures low operating power. TTL compatibility over the full military temperature range and bus hold circuitry eliminate the need for pull-up resistors. The Harris advanced SAJI process results in performance equal to or greater than existing functionally equivalent products at a fraction of the power Ordering Information PART NUMBERS 5MHz CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. File Number

VCC: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is recommended for decoupling. RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the “Bus Hold” circuitry turned on. CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU communications. READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus. WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A. ADDRESS:...

82C55A Functional Description Data Bus Buffer POWER SUPPLIES This three-state bi-directional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both...

82C55A Ports A, B, and C The 82C55A contains three 8-bit ports (A, B, and C). All can be congured to a wide variety of functional characteristics by the system software but each has its own special features or “personality” to further enhance the power and exibility of the 82C55A. program, any of the other modes may be selected using a single output instruction. This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine. Any port programmed as an output port is initialized to all zeros when the control word is written. ADDRESS BUS Port A...

82C55A The modes for Port A and Port B can be separately dened, while Port C is divided into two portions as required by the Port A and Port B denitions. All of the output registers, including the status ip-ops, will be reset whenever the mode is changed. Modes may be combined so that their functional denition can be “tailored” to almost any I/O structure. For instance: Group B can be programmed in Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt-driven basis. The mode denitions...

82C55A Mode 0 (Basic Input) tRR Mode 0 (Basic Output) tWW WR tWD Mode 0 Congurations CONTROL WORD #0

Operating Modes Mode 1 - (Strobed Input/Output). This functional conguration provides a means for transferring I/O data to or from a specied port in conjunction with strobes or “hand shaking” signals. In mode 1, port A and port B use the lines on port C to generate or accept these “hand shaking” signals. Mode 1 Basic Function Denitions: • Two Groups (Group A and Group B) • Each group contains one 8-bit port and one 4-bit control/data port • The 8-bit data port can be either input or output. Both inputs and outputs are latched. • The 4-bit port is used for control and status of the 8-bit port....

RD tPH INPUT FROM PERIPHERAL tPS FIGURE 7. MODE 1 (STROBED INPUT) INTR (Interrupt Request) A “high” on this output can be used to interrupt the CPU when and input device is requesting service. INTR is set by the condition: STB is a “one”, IBF is a “one” and INTE is a “one”. It is reset by the falling edge of RD. This procedure allows an input device to request service from the CPU by simply strobing its data into the port. INTE A Controlled by bit set/reset of PC4. INTE B Controlled by Bit Set/Reset of PC2. NOTE: To strobe data into the peripheral device, the user must operate the strobe line...

FIGURE 9. MODE 1 (STROBED OUTPUT) ACKA INTRA PORT A - (STROBED INPUT) PORT B - (STROBED OUTPUT) PORT A - (STROBED OUTPUT) PORT B - (STROBED INPUT) Combinations of Mode 1: Port A and Port B can be individually dened as input or output in Mode 1 to support a wide variety of strobed I/O applications. FIGURE 10. COMBINATIONS OF MODE 1 Operating Modes Mode 2 (Strobed Bi-Directional Bus I/O) Output Operations The functional conguration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bi-directional bus I/O). “Hand...

PORT B 1 = INPUT 0 = OUTPUT WR GROUP B MODE 0 = MODE 0 1 = MODE 1 FIGURE 11. MODE CONTROL WORD WR tAOB OBF tWOB INTR tAK ACK tST STB DATA FROM PERIPHERAL TO 82C55A DATA FROM 82C55A TO PERIPHERAL DATA FROM 82C55A TO CPU NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF • MASK • STB • RD ÷ OBF • MASK • ACK • WR) FIGURE 13. MODE 2 (BI-DIRECTIONAL)