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Xcelera-CL VX4

Xcelera-CL VX4
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Xcelera-CL VX4 Full - Next Generation Vision Processor Boards The Xcelera-CL VX4 is the next generation user programmable vision processor based on the PCI Express X4 platform. It features powerful embedded processing architecture for real-time high-performance machine vision applications. Combining high-speed image acquisition capability with user programmable FPGAs (Field Programmable Gate Array) and graphical FPGA development tools, our vision processors deliver unmatched power and flexibility in real-time image processing on the PCIe platform. The X64 Xcelera-CL VX4 Full is a Camera Link vision processor that is based on the PCI Express x4 interface. Compatible with a Base, Medium or Full Camera Link camera, the X64 Xcelera-CL VX4 Full supports a wide variety of multi-tap area and line scan colour and monochrome cameras. The X64 Xcelera-CL VX4 Full board can interface with advanced Camera Link cameras output formats including 10-taps of 8-bit at 85MHz pixel clock rates. ® Features • Half-length PCI Express x4 Board • Acquires images from one Base, Medium or Full Camera Link camera • eal-time FPGA based hardware R processing • User programmable FPGA tools • upports Camera Link S operations up to 85MHz • xtended feature set supports E advanced Camera Link pixel/tap configurations • indows XP and Windows 7 W (32/64-bit) compatible • ully Supported by Sapera APF F and Sapera Vision Software SDKs • FCC, CE and ROHS compliant Sophisticated Embedded Processing Platform The Xcelera-CL VX4 Full feature an FPGA hardware processing platform that combines ACU(Acquisition Control Unit), DTE (Data Transfer Engine) and IPU (Image Processing Unit) and state of the memory architecture. As a result, models such as our new Xcelera-CL VX4 are capable of handling variety of complex, real-time image processing topologies including iterative processing loops. While the FPGA technology provides ability to adapt to variety of highspeed, compute-intensive real-time processing applications, the Xcelera VX4 hardware design has been implemented using standard off-the-shelf components with long term availability. Frame Buffer Memory 2x512 MB Image Processing Memory 4x32 MB Image Processing Unit (IPU) Camera Input Camera Control Aquisition Control Unit (ACU) PCIe x4 INTERFACE Simplified Hardware Architecture User FPGA Code

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Xcelera-CL VX4 Full Function Camera Link Specifications Rev 1.2 compatible Half length PCI Express 1.1 x4 compliant ROHS Compliant Supports one Base, Medium or Full Camera Link area and line scan camera Acquisition pixel clock rates from 20MHz to 85MHz Horizontal Size (min/max): 16 byte/64K bytes Comprehensive event notification includes start/end of frame/transfer Camera control signals for external event synchronization Optically isolated trigger inputs programmable as active high or low (edge or level trigger) TTL Strobes outputs PC independent serial communications ports provide support...

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