CMX983 CML Microcircuits COMMUNICA TION SEMICONDUCTORS Analogue Front End (AFE) for Digital Radio Advance Information Features Rx channel Two 16-bit Σ-Δ A/D Converters Programmable Channel Filter Tx Channel Two 14-bit Σ-Δ D/A Converters Programmable Channel Filter RF Support Two 2.1GHz Fractional-N Synthesisers Auxiliary Functions 10-bit A/D Converter supporting 10 inputs Five Analogue Comparators 10-bit D/A Converters driving 9 outputs DSP Interface C-BUS Control and Configuration Port Fast Serial Interface for Rx/Tx Data Duplex and Half duplex operation Direct connection to: CMX998 Cartesian Loop Transmitter CMX994 Direct Conversion Receiver Low power operation 3.3V and 1.8v supplies Small 64-pin VQFN Package Software Defined Radio (SDR) Satellite Communication Wireless Data Terminals Digital PMR/LMR Radio TETRA DMR PDT

Analogue Front End (AFE) for Digital Radio Brief Description The CMX983 is an Analogue Front End (AFE) IC that bridges the gap between a digital radio’s RF section and the DSP. Specifically designed to meet the needs of a Software Designed Radio (SDR), the CMX983 performs critical DSP-intensive functions, provides dual channel analogue to digital and digital to analogue conversion, includes two RF fractional-N synthesisers, and embeds a host of auxiliary ADCs and DACs for use within the radio system. The CMX983 meets the low operating power requirements of SDR-based terminals and is powered from...

Analogue Front End (AFE) for Digital Radio CONTENTS Section

Analogue Front End (AFE) for Digital Radio Table Table 1 Table 2 Table 3 Table 4

Analogue Front End (AFE) for Digital Radio Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 It is always recommended that you check for the latest product datasheet version from the Datasheets page of the CML website: [www.cmlmicro.com].

Analogue Front End (AFE) for Digital Radio Changes Section 15.3 (Operating Characteristics), Synthesiser 1 and 2, RF Input Sensitivity: Note 12 added, providing additional clarification and qualification to the stated figures. Section 15.5 – Typical Performance Characteristics added Section 12 – Diagram modified, advice regarding connection to single ended VCO added Section 12 – PLL1_CON and PLL2_CON bits 13-11 description expanded Section 12 – PLL1_FLCK and PLL2_FLCK bits 1-0 description expanded Section 12 – PLL1_BLEED and PLL2_BLEED guidelines added Section 12.2 – References to modulator type...

Analogue Front End (AFE) for Digital Radio CALI CALQ Input Switch Serial Ports sincN/ decimate sincN/ decimate Upsample/ hold Upsample/ interpolate Upsample/ hold Upsample/ interpolate PLL1 Frac-N divider Charge pump Phase detect * AVSS is connected directly to the metal pad on the underside of the package MCLK RESETN PLL2 Frac-N divider Charge pump C-BUS Configuration and Control Phase detect DVDD (1.8V) DVSS IOVDD (3.3V) IOVSS AVDD (3.3V) AVSS* SCLK CSN CDATA RDATA IRQN VBIAS VBBUF Figure 1 Block Diagram

Analogue Front End (AFE) for Digital Radio General Description The CMX983 is an Analogue Front End (AFE) for a DSP used in Software Defined Radio systems and acts as a bridge between the analogue and digital sections of advanced digital radio systems. The device also performs critical DSP-intensive functions with low operating power thereby reducing the overall system power consumption. The receive path accepts differential analogue baseband I/Q signals. These are converted to digital, decimated and passed through programmable FIR channel filters to simplify host DSP processing and data extraction....

Analogue Front End (AFE) for Digital Radio VBBUF VBIAS The exposed metal pad at the underside of the package must connect to AVSS Figure 2 CMX983Q1 Pin Arrangement (top view)

Analogue Front End (AFE) for Digital Radio Table 1 Pin and Signal List Package Q1 Pin Name Pin No. Signal Description I channel positive input I channel negative input Q channel positive input Q channel negative input Positive output for I channel Negative output for I channel Positive output for Q channel Negative output for Q channel Auxiliary DAC 7 output (Auxiliary ADC 6 input can be selected) Auxiliary DAC 8 output (Auxiliary ADC 7 input can be selected) Core power (1.8V) Serial port receive data Internally generated bias voltage of VDDA/2 Serial port receive frame sync

Analogue Front End (AFE) for Digital Radio Signal Description Serial port receive clock Serial port transmit data Serial port transmit frame sync Serial port transmit clock C-BUS serial clock input from the µC C-BUS serial data output (3-state) to the µC C-BUS serial data input from the µC C-BUS chip select input (active low) from the µC C-BUS interrupt request (open drain, active low) to the µC PLL1 charge pump output PLL1 charge pump input supply PLL2 charge pump input supply PLL2 charge pump output Master clock input I channel test calibration input Q channel test calibration input Buffered...

Analogue Front End (AFE) for Digital Radio 3-state Output Power Connection No Connection Table 2 Definition of Power Supply and Reference Voltages Signal Name Pins Usage VDD Analogue, AVDD AVDD 3.3V positive supply rail for the analogue circuits VBIAS VBIAS Internal analogue reference level, derived from AVDD VBBUF VBBUF Buffered mid-rail reference voltage (=AVDD /2) VDD RF, RF1VDD, RF2VDD RF1VDD, RF2VDD 1.8V positive supply rail for RF power VDD Charge Pump, CP1VDD, CP2VDD <5.0V positive supply rail for the Charge Pumps CP1VDD, CP2VDD VSS Analogue, AVSS AVSS Ground for all analogue circuits...

Analogue Front End (AFE) for Digital Radio Figure 4 Power Supply Decoupling To achieve good noise performance, VDD and VBIAS decoupling and protection of the receive path from extraneous in-band signals are very important. It is recommended that the printed circuit board is laid out with ground planes in the CMX983 area to provide a low impedance connection between the VSS pins and the VDD and VBIAS decoupling capacitors. 100nH inductors or 10Ω resistors, in combination with 10nF capacitors, should be used to decouple the power supplies, as shown in Figure 4.