CML Microcircuits COMMUNICA TION SEMICONDUCTORS 7261FI-2.x – G.723.1 Full Duplex Codec DATASHEET • Half-duplex operation Full-duplex operation Codec support: o G.723.1 codec (5.3kbps / 6.3kbps rates) with Annex A o PCM (linear, µ-law, A-law), • Transcoding support: o PCM to G.723.1 and reverse o PCM μ/A/linear to PCM μ/A/linear transcoder • No external DSP or codecs required: simply upload Function Image™ (FI) • Transcoder routing: o Choice of input sources – C-BUS transfer to host, external PCM device/codec, analogue audio input o Choice of output sources – C-BUS transfer to host, external PCM device/codec, analogue audio output Advance Information C-BUS host serial interface o SPI-like with register addressing o Read/Write 128-word FIFOs and data buffers to streamline transfers and relax host service latency Auxiliary functions o Three GPIOs o Analogue input/output gain adjustment o Analogue input multiplexer o Analogue output multiplexer Master/Slave PCM serial interface o For external audio CODEC Low power 3.3V operation with powersave functions Small 64-pin VQFN or LQFP package Half duplex digital radio systems Full duplex digital radio systems Personal area network voice links Privacy-type digital voice communications Wireless PBX VoIP applications Digital Software Defined Radio (SDR) Digital Filters Digital Filters FIFO Configuration

Brief Description The CMX7261 Multi-transcoder IC is a device supporting multiple speech codecs in a single chip. When loaded with FI-2.x the CMX7261 is capable of encoding analogue voice into PCM (linear, µ-law or A-law) or G.723.1 data formats at either 5.3kbps or 6.3kbps. It is capable of decoding PCM or G.723.1 (both rates) back to analogue voice. It can also transcode data between PCM formats and G.723.1. Input and output signals may be passed through the C-BUS interface, the PCM port or the on-chip converters (ADC/DAC). The device utilises CML’s proprietary FirmASIC component technology....

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Full public release, minor typographical corrections First public release Advance Draft for first alpha release Information in this data sheet should not be relied upon for final product design. It is recommended that you check for the latest product datasheet version from the CML website: [www.cmlmicro.com].

Block Diagrams Half Duplex Transcoder Decoder output is 16-bit linear PCM Transcoder Half Duplex (detailed view) Select one using Input_Type C-BUS reg Pass Through Pass Through Select one using Output_Type C-BUS reg Audio Filter Fine Gain Audio Filter Encoder Output Buffer Input Buffer Transcoder Block IRQN Audio_In FIFO Host Thru Commands Audio_Out FIFO CDATA SCLK External serial memory boot C-BUS Interface Auxiliary Functions GPIOA GPIOB FI Configured I/O Power control Main Clock PLL Boot Control System Clock Crystal Oscillator XTAL/ CLOCK Figure 1 Block Diagram Figure 1 presents a detailed...

Input audio stream Input Port-A Output Port-B Output audio stream Output audio stream Output Port-A Input Port-B Input audio stream Figure 2 Full Duplex Block Diagram In full duplex operation, the input and output ports may be specified on one channel and the opposite input and output ports will be used for the second channel. Table 1 shows the mapping between Input Ports and Output Ports. Table 1 Input and Output Ports – Full Duplex Mapping Input Port-A / B Analogue In Audio In FIFO (C-BUS In) PCM Port In Output Port-A / B Analogue Out Audio Out FIFO (C-BUS Out) PCM Port Out For example, if...

Signal Description The combined state of BOOTEN1 and BOOTEN2, upon RESET, determine the Function Image™ load interface. The combined state of BOOTEN1 and BOOTEN2, upon RESET, determine the Function Image™ load interface. Negative supply rail (ground) for the digital on-chip circuits. 3.3V positive supply rail for the digital on-chip circuits. This pin should be decoupled to DVSS by capacitors mounted close to the supply pins. Logic input used to reset the device (active low). Negative supply rail (ground) for the digital on-chip circuits. Single ended output for speaker. Positive 3.3V supply...

Signal Description NC Internally generated bias voltage of approximately AVDD/2. If VBIAS is power saved this pin will present a high impedance to AVDD. This pin must be decoupled to AVSS by a capacitor mounted close to the device pins; no other connections should be made. Differential inputs for main audio; ‘P’ is positive, ‘N’ is negative. Together these are referred to as the ANAIN. ADC reference voltage; connect to AVSS. Positive 3.3V supply rail for the analogue on-chip circuit. Levels and thresholds within the device are proportional to this voltage. This pin should be decoupled to AVSS...

Signal Description Negative supply rail (ground) for the digital on-chip circuits. Output of the on-chip xtal oscillator inverter. Input to the oscillator inverter from the xtal circuit or external clock source. C-BUS serial clock input from the µC. 3-state C-BUS serial data output to the µC. This output is high impedance when not sending data to the µC. C-BUS serial data input from the µC. C-BUS chip select input from the µC. ‘wire-Orable’ output for connection to the Interrupt Request input of the µC. This output is pulled down to DVSS when active and is high impedance when inactive. An external...

Notes: IP = Input (+ PU/PD = internal pull-up / pull-down resistor) NC = No Connection - should NOT be connected to any signal Table 2 Definition of Power Supply and Reference Voltages

PCB Layout Guidelines and Power Supply Decoupling + CLKI DVDD RESETN DVSS GPIOB GPIOC DVSS Active low reset from supervisor IC or RC circuit Digital Ground Plane Analogue Ground Plane Figure 3 CMX7261 Power Supply and De-coupling Notes: To achieve good noise performance, VDD and VBIAS decoupling and protection of the receive path from extraneous in-band signals are very important. It is recommended that the printed circuit board is laid out with a ground plane in the CMX7261 area to provide a low impedance connection between the VSS pins and the VDD and VBIAS decoupling capacitors.