CS4953xx
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CS4953xx Data Sheet FEATURES Audio Decoder DSP Family with Dual 32-bit DSP Engine Technology  Multi-standard 32-bit Audio Decoding plus Post processing  Supports legacy audio formats and a wide array of postprocessing — Dolby Digital® EX, Dolby Pro Logic® II, IIx, IIz 7.1, Dolby Headphone® 2, Dolby Virtual Speaker® 2, Dolby Volume® (original), Dolby Volume 258™ (lite), Audistry® — DTS-ES 96/24™ Discrete 7.1, DTS-ES™ Discrete 7.1, DTS-ES™ Matrix 6.1, DTS Neo:6®, DTS Neural Surround™ DTS Surround Sensation Speaker — MPEG-2 AAC™ LC 5.1 — SRS® Circle Surround® II, SRS Circle Surround Auto, SRS Circle Surround Decoder Optimized, SRS TruVolume™ 7.1 (V 2.1.0.0), SRS TruSurround HD/HD4®, SRS WOW HD™, SRS CS Headphone™, SRS Circle Cinema 3D™, SRS Studio Sound HD™ — THX® Ultra2™, THX Select2™  Cirrus Logic’s Applications Library — Cirrus Original Multi-Channel Surround 2 (COMS2), Cirrus Band XpandeR™, Cirrus Virtualization Technology (CVT), Cirrus Intelligent Room Calibration 2 (IRC2), Cirrus Bass Enhancement (CBE) — Crossbar Mixer, Signal Generator — Advanced Post-Processors including: 7.1 Bass Manager Quadruple Crossover, Tone Control, 11Band Parametric EQ, Delay, 2:1/4:1 Decimator, 1:2/1:4 Upsampler  Up to 12 Channels of 32-bit Serial Audio Input 16 Ch x 32-bit PCM Out with Dual 192 kHz S/PDIF Tx Two SPI™/I2C™ Ports Customer Software Security Keys Large On-chip X, Y, and Program RAM & ROM SDRAM and Serial Flash Memory Support The CS4953xx DSP family are the enhanced versions of the CS495xx DSP family with higher overall performance and lower system cost. The CS4953xx includes all mainstream audio processing codes in on-chip ROM. This saves external memory for code storage. In addition, the intensive decoding tasks of Dolby Digital Surround EX®, AAC multi-channel, DTS-ES 96/24, THX Ultra2 Cinema and Dolby Headphone can be accomplished without the expense of external SDRAM memory. With larger internal memories than the CS495xx, the CS49531x is designed to support up to 150 ms per channel of lip-sync delay. With 150 MHz internal clock speed, the CS4953xx supports the most demanding post-processing requirements. It is also designed for easy upgrading. Customers currently using the CS495xx can upgrade to the CS4953xx with minor hardware and software changes. Ordering Information See page 28 for ordering information. Parallel Control S/PDIF S/PDIF 16 Ch PCM Audio Out Ext. Memory Controller

CS4953xx Data Sheet 32-bit Audio Decoder DSP Family

CS4953xx Data Sheet 32-bit Audio Decoder DSP Family List of Tables Table 1. CS4953xx Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. CS49530x DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. CS49531x DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . ....

rCIRRUS LOGIC CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 1 Documentation Strategy The CS4953xx data sheet describes the CS4953xx family of multichannel audio decoders. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS4953xx family of processors. Table 1. CS4953xx Related Documentation The scope of the CS4953xx data sheet is primarily the hardware specifications of the CS4953xx family of devices. This includes hardware functionality, characteristic data, pinout, and packaging information. The intended...

CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 2.1 Migrating from CS4953x3 to CS4953x4 • The recommended way to boot the DSP for normal operation is “master boot”. Refer to Chapter 1 of the CS4953x4/CS4970x4 System Designer’s Guide. CS4953x4 supports slave boot mode as well (used for programming the serial flash with the DSP code, through the SCP2 port). • CS4953x4 DSPs are only available in 128 pin package. • The serial flash chip select pin used is pin 14 (GPIO0) for master boot. Cirrus Logic recommends that at least an 8-Mb serial flash device be used. Refer to CS4953x4/CS4970x4...

rCIRRUS LOGIC CS4953xx Data Sheet 32-bit Audio Decoder DSP Family Table 2. Device and Firmware Selection Guide1 I.This feature list is a snapshot of features available as of the publication date of this revision of the data sheet. More features may now be available. Check with your Cirrus Logic Field Application Engineer (FAE) to obtain the latest feature list for the CS49530x and CS49531x products. 2. Additional processing (MPMA, MPMB, VPM, PPM) post any of the HD audio decoders may be limited. Contact your Cirrus Logic FAE for concurrency matrix.

rCIRRUS LOGIC CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 4 Hardware Functional Description 4.1 Coyote 32-bit DSP Core The CS4953xx is a dual-core DSP with separate X and Y data and P code memory spaces. Each core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply accumulate (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four X- and four Y-data registers, and 12 index registers. Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals such as the digital...

CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 4.2 On-chip DSP Peripherals 4.2.1 Digital Audio Input Port (DAI) The 12-channel (6-line) DAI port supports a wide variety of data input formats. The port is capable of accepting PCM or IEC61937. Up to 32-bit word lengths are supported. The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which off-loads the task of monitoring the S/PDIF receiver from the host. A time-stamping feature...