CS43131
156Pages

CS43131 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver and Impedance Detection System Features Interrupt Sources Digital LDOs Interpolation Filter and Volume Control XSP/DSD Audio Interface Register /Hardware Configuration FLYC_VCP FLYP_VCP FLYN _VCP VCP_FILT+ VCP_FILT FLYP_VA FLYN_VA -VA DSD Processor Popguard® Circuitry Control Port Level Translator Copyright  Cirrus Logic, Inc. 2015–2017 (All Rights Reserved) Charge Pump Interpolation Filter and Volume Control Analog Supply (VA,VCP) Battery Supply +1.8V (VP) Internal Voltage Reference FILT+ FILT- Digital Core Internal Interface Supply (VL) Supply (VD) +1.8V +1.8V Level Translator • Direct Stream Digital (DSD®) path — Up to 256•Fs DSD Enhanced  oversampling DAC architecture — Patented DSD processor — 32-bit resolution – On-chip 50-kHz filter to meet Scarlet Book Super — Up to 384-kHz sampling rate Audio Compact Disk (SACD) recommendations — Low clock jitter sensitivity – Matched PCM and DSD analog output levels — Auto mute detection – Nondecimating volume control with 0.5-dB step size Integrated high performance, ground-centered stereo and soft ramp headphone outputs – DSD and Pulse-code modulation (PCM) mixing for — 130-dB dynamic range (A-weighted) alerts — –115-dB total harmonic distortion + noise (THD+N) — Dedicated DSD and DoP pin interface — 110-dB interchannel isolation • Serial audio input path — Up to 2-Vrms stereo output — Programmable Hi-Fi digital filter — Headphone power output — Five selectable digital filter responses – 30 mW per channel into 32  – Low-latency Mode minimizes pre-echo – 5 mW per channel into 600  – 110 dB of stopband attenuation Headphone detection — Supports sample rates from 32 to 384 kHz — Headphone DC and AC impedance measurement — I2S, right-justified, left-justified, TDM, and — Headphone plug-in detection DSD-over-PCM (DoP) interface — Popguard® technology eliminates pop noise — Master or slave operation Integrated PLL — Volume control with 0.5-dB step size and soft ramp — Support for 11.2896-/22.5792-, 12.288-/24.576-, 9.6-/ — 44.1 kHz deemphasis and inverting feature 19.2-, 12-/24-, and 13-/26-MHz system MCLK rates • Alternate headphone input — Reference clock sourced from XTI/MCLK pin • 40-pin 5mm × 5mm QFN or 42-ball CSP package options — System clock output Applications Mono Mode (differential) support • Smart phones, tablets, portable media players, laptops, I2C control—up to 1 MHz digital headphones, powered speakers, AVR, home Wideband Flatness Mode Support theater systems, Blu-ray/

CS43131 General Description The CS43131 is a high-performance, 32-bit resolution, stereo audio DAC that supports up to 384-kHz sampling frequency with integrated low-noise ground-centered headphone amplifiers. The advanced 32-bit oversampled multibit modulator with mismatch shaping technology eliminates distortion due to on-chip component mismatch. Proprietary digital-interpolation filters support five selectable filter responses with pseudo-linear phase and ultralow latency to minimize pre-echos and ringing artifacts. An on-chip programmable filter is available for further response...

CS43131 Table of Contents 1 Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . 4 1.1 40-Pin QFN (Top-Down, Through-Package View) . . . . . . . . . 4 1.2 42-Ball WLCSP (Top-down, Through-Package View) . . . . . . 5 1.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 Electrostatic Discharge (ESD) Protection Circuitry . . . . . . . . 8 2 Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . 12 Table 3-1. Parameter...

CIRRUS LOGIC CS43131 1 Pin Assignments and Descriptions 1 Pin Assignments and Descriptions 1.1 40-Pin QFN (Top-Down, Through-Package View) Q w < Q W Q RESET INT VP VCP FLYP_VCP FLYC_VCP HP_DETECT VCP_FILT+ Figure 1-1. Top-Down (Through-Package) View—QFN 40-Pin Diagram

1.2 42-Ball WLCSP (Top-down, Through-Package View) 1.2 42-Ball WLCSP (Top-down, Through-Package View) Charge Pump Power Supplies Figure 1-2. Top-Down (Through-Package) View—42-Ball WLCSP Package

I.The power supply is determined by ADPT_PWR setting (see Section 4.3.1). VP is used if ADPT_PWR = 001 (VP_LDO Mode) or when necessary for ADPTPWR = 111 (Adapt-to-Signal Mode).

1.4 Electrostatic Discharge (ESD) Protection Circuitry 1.4 Electrostatic Discharge (ESD) Protection Circuitry ESD-sensitive device. The CS43131 is manufactured on a CMOS process. Therefore, it is generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken while handling and storing this device. This device is qualified to current JEDEC ESD standards. Fig. 1-3 provides a composite view of the ESD domains showing the ESD protection paths between each pad and the substrate (GND), as well as the interrelations between some domains. Note that this...

CIRRUS LOGIC CS431311.4 Electrostatic Discharge (ESD) Protection Circuitry Table 1-2. ESD Domains (Cont.) ESD Domain

2 Typical Connection Diagram 2 Typical Connection Diagram VL Audio Codec Headphone Output Applications Processor/ MicroController HPOUTB Headphone Connector HP_DETECT RESET PCM/DoP Digital Audio Source DoP/DSD Digital Audio Source Audio Devices Note 1 All external passive component values shown are nominal . Clocking Configuration XTAL External MCLK System Clock Key for Capacitor Types Required : * Use low ESR, X7R/X5R capacitors If no type symbol is shown next to a capacitor, any type may be used. ** Use C0G capacitors. VCP_FILT Configuration EXT_VCPFILT = 0 VCP_FILT+ VCP_FILT– GNDCP...

2 Typical Connection Diagram VL Audio Codec Headphone Output PCM/DoP Digital Audio Source Applications Processor/ MicroController HPREFA RESET DoP/DSD Digital Audio Source Audio Devices Note 1 All external passive component values shown are nominal. Clocking Configuration XTAL External MCLK System Clock Key for Capacitor Types Required: * Use low ESR, X7R/X5R capacitors If no type symbol is shown next to a capacitor, any type may be used. ** Use C0G capacitors. VCP_FILT Configuration EXT_VCPFILT = 0 VCP_FILT+ VCP_FILT– GNDCP VCP_FILT– GNDCP Figure 2-2. Typical Connection Diagram (Mono Mode)...