CS43130
137Pages

CS43130 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver and Impedance Detection System Features Interrupt Sources Interpolation Filter and Volume Control Interpolation Filter and Volume Control XSP/DSD Audio Interface DSD Processor Popguard® Circuitry Control Port Level Translator FLYC_VCP FLYP_VCP FLYN _VCP VCP_FILT+ VCP_FILT FLYP_VA FLYN_VA -VA Register /Hardware Configuration Copyright  Cirrus Logic, Inc. 2015–2016 (All Rights Reserved) Charge Pump Analog Supply (VA,VCP) Battery Supply +1.8V (VP) Internal Voltage Reference Digital Core FILT+ FILT- Digital LDOs Internal Interface Supply (VL) Supply (VD) +1.8V +1.8V Level Translator • Direct Stream Digital (DSD®) path — Patented DSD processor Enhanced  oversampling DAC architecture – On-chip 50-kHz filter to meet Scarlet Book Super — 32-bit resolution Audio Compact Disk (SACD) recommendations — Up to 384-kHz sampling rate – Matched PCM and DSD analog output levels — Low clock jitter sensitivity – Nondecimating volume control with 0.5-dB step size — Auto mute detection and soft ramp Integrated high performance, ground-centered stereo – DSD and Pulse-code modulation (PCM) mixing for headphone outputs alerts — 130-dB dynamic range (A-weighted) — Dedicated DSD and DoP pin interface — –108-dB total harmonic distortion + noise (THD+N) • Serial audio input path — 110-dB interchannel isolation — Five selectable digital filter responses — Headphone power output – Low-latency mode minimizes pre-echo – 30 mW per channel into 32  – 110 dB of stopband attenuation – 5 mW per channel into 600  — Supports sample rates from 32 to 384 kHz Headphone detection — I2S, right-justified, left-justified, TDM, and — Headphone DC and AC impedance measurement DSD-over-PCM (DoP) interface — Headphone plug-in detection — Master or slave operation — Popguard® technology eliminates pop noise — Volume control with 0.5-dB step size and soft ramp Integrated PLL — 44.1 kHz deemphasis and inverting feature — Support for 11.2896-/22.5792-, 12.288-/24.576-, 9.6-/ • Alternate headphone input 19.2-, 12-/24-, and 13-/26-MHz system MCLK rates • 40-pin QFN or 42-ball CSP package option — Reference clock sourced from XTI/MCLK pin Applications — System clock output • Smart phones, tablets, portable media players, laptops, Mono mode support digital headphones, powered speakers, AVR, home I2C control—up to 1 MHz theater systems, Blu-ray/DVD/SACD p

CS43130 General Description The CS43130 is a high-performance, 32-bit resolution, stereo audio DAC that supports up to 384-kHz sampling frequency with integrated low-noise ground-centered headphone amplifiers. The advanced 32-bit oversampled multibit modulator with mismatch shaping technology eliminates distortion due to on-chip component mismatch. Proprietary digital-interpolation filters support five selectable filter responses with pseudo-linear phase and ultralow latency to minimize pre-echos and ringing artifacts. Other features include volume control with 0.5-dB steps and digital...

CS43130 Table of Contents 1 Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . 4 1.1 40-Pin QFN (Top-Down, Through-Package View) . . . . . . . . . 4 1.2 42-Ball WLCSP (Top-down, Through-Package View) . . . . . . 5 1.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 Electrostatic Discharge (ESD) Protection Circuitry . . . . . . . . 8 2 Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . 11 Table 3-1. Parameter...

CIRRUS LOGIC CS43130 1 Pin Assignments and Descriptions 1 Pin Assignments and Descriptions 1.1 40-Pin QFN (Top-Down, Through-Package View) Q co < a co a RESET INT VP VCP FLYP_VCP FLYC_VCP HP_DETECT VCP_FILT+ Figure 1-1. Top-Down (Through-Package) View—QFN 40-Pin Diagram

1.2 42-Ball WLCSP (Top-down, Through-Package View) 1.2 42-Ball WLCSP (Top-down, Through-Package View) Charge Pump Power Supplies Figure 1-2. Top-Down (Through-Package) View—42-Ball WLCSP Package

I.The power supply is determined by ADPT_PWR setting (see Section 4.3.1). VP is used if ADPT_PWR = 001 (VP_LDO Mode) or when necessary for ADPTPWR = 111 (Adapt-to-Signal Mode).

1.4 Electrostatic Discharge (ESD) Protection Circuitry 1.4 Electrostatic Discharge (ESD) Protection Circuitry ESD-sensitive device. The CS43130 is manufactured on a CMOS process. Therefore, it is generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken while handling and storing this device. This device is qualified to current JEDEC ESD standards. Fig. 1-3 provides a composite view of the ESD domains showing the ESD protection paths between each pad and the substrate (GND), as well as the interrelations between some domains. Note that this...

1.4 Electrostatic Discharge (ESD) Protection Circuitry Table 1-2. ESD Domains (Cont.) ESD Domain VA/–VA Signal Name (See * in Topology Figures for Pad) FLYN_VA FLYP_VA FILT+ FILT– INT VP/VCP_FILT– FLYP_VCP FLYC_VCP HP_DETECT VCP_FILT+/ FLYN_VCP VCP_FILT– HPINA HPINB HPOUTA HPOUTB HPREFA HPREFB VP/GNDCP Domain VCP_FILT+/VCP_FILT– Domain VP/VCP_FILT– Domain

2 Typical Connection Diagram 2 Typical Connection Diagram VL HPOUTB Headphone Connector HP_DETECT RESET Applications Processor/ MicroController Audio Codec Headphone Output PCM/DoP Digital Audio Source DoP/DSD Digital Audio Source Audio Devices All external passive component values shown are nominal . Clocking Configuration XTAL External MCLK System Clock Key for Capacitor Types Required : * Use low ESR, X7R/X5R capacitors If no type symbol is shown next to a capacitor, any type may be used. ** Use C0G capacitors. VCP_FILT Configuration EXT_VCPFILT = 0 VCP_FILT+ VCP_FILT– GNDCP VCP_FILT+...