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CS43130

Product catalog summary

Overview: The CS43130 is a high-performance, 32-bit stereo audio DAC designed for high-resolution audio playback, supporting sampling frequencies up to 384 kHz. It integrates low-noise, ground-centered headphone amplifiers.

Key Features:

DAC Architecture: Utilizes a 32-bit oversampled multibit modulator with mismatch shaping technology to reduce distortion.
Headphone Amplifiers: Delivers 30 mW into a 32-Ω load or 5 mW into a 600-Ω load per channel.
Impedance Detection: Proprietary headphone impedance detection for enhanced digital post-processing.
DSD Processor: On-chip DSD processor for direct signal processing without intermediate decimation.
Audio Interfaces: Supports I2S, right-justified, left-justified, and TDM-format PCM data at sample rates from 32 to 384 kHz.
Control Interface: Configurable via a high-speed I2C interface up to 1 MHz.
Clocking Flexibility: Integrated PLL for flexible clocking and Popguard® technology to eliminate output transients.

Applications: Suitable for smartphones, tablets, portable media players, laptops, digital headphones, powered speakers, AVR, home theater systems, Blu-ray/DVD/SACD players, and professional audio equipment.

Specifications:

Dynamic Range: 130 dB (A-weighted)
THD+N: -108 dB
Interchannel Isolation: 110 dB
Package Options: Available in 42-ball WLCSP or 40-pin QFN packages.

Functional Description: The CS43130 integrates advanced digital-interpolation filters with selectable filter responses to minimize pre-echo and ringing artifacts. It includes volume control with 0.5-dB steps and digital deemphasis for 44.1-kHz sample rates.

Additional Features: Supports mono mode, alternate headphone input paths, and includes a system clock output. Features a direct stream digital (DSD) path with a dedicated DSD and DoP pin interface.

Procedures and Test Conditions:

Test conditions include a 32-bit, full-scale 997-Hz sine wave input, with various load resistances and capacitances specified for different tests.
Measurements are taken with specific voltage and temperature conditions, typically at +25°C.
Various operational modes are tested, including single-speed, double-speed, quad-speed, and octuple-speed modes, each with specific filter characteristics.

Filter Characteristics:

Fast and slow roll-off filters characterized by their passband, stopband, and group delay, with specifications varying by operational mode.
Nonoversampling (NOS) mode detailed with specific passband and group delay characteristics.

Recommendations:

Ensure proper configuration of volume and operational modes to achieve specified output characteristics.
Follow specified test conditions for accurate measurement and performance evaluation.

Specifications and Parameters: The document outlines various electrical characteristics and specifications for the device, including input leakage current, internal weak pull-down resistance, input capacitance, and logic levels for both non-I2C and I2C logic.

CLKOUT and PLL Characteristics: Details on output frequency, duty cycle, and jitter, while the PLL section describes output frequency, lock time, and reference clock input requirements.

Crystal and PSRR Characteristics: Crystal characteristics include oscillator frequency, load capacitance, and startup time. PSRR characteristics are detailed for various frequencies and supply conditions.

DC Characteristics and Power Consumption: DC characteristics cover various voltage levels and operational amplifier specifications. Power consumption is detailed for different use cases, such as off, standby, and playback modes.

Serial-Port Interface and I2C Characteristics: Outlines timing requirements for master and slave modes, including frame rate, duty cycle, and setup/hold times. I2C characteristics specify clock frequency, timing for start/stop conditions, and bus capacitance.

Functional Description: Provides an overview of the device's operation, including analog outputs, class H amplifier output, headphone inputs, clocking architecture, and audio serial port.

System Clocking: Internal MCLK can be sourced from direct MCLK/crystal mode, PLL mode, or RCO mode, with specific features supported in each mode.

System Interrupts and Reset: Includes an open-drain interrupt output with mask registers to control event-triggered interrupts. Offers two reset options: asserting RESET and power-on reset (POR).

Power Down and Analog Outputs: Allows individual components to be powered down via register settings. The analog output is derived from digital audio input ports, with signal flow and volume control options detailed.

Class H Amplifier Output: Uses Class H technology to maximize efficiency by varying rail voltages according to the music passage needs.

Power-Supply Transitions and Current Limiter: Charge-pump transitions between rail voltages are managed to prevent clipping and ensure smooth operation.

External VCP_FILT Supply Mode: External VCP_FILT± supply can bypass the internal charge-pump circuit under specific conditions to avoid damage.

External VCP_FILT Power-Up Sequence: To power up the CS43130 in this mode, follow the recommended sequence starting from a Hi-Z state on the VCP_FILT± pins.

External VCP_FILT Power-Down Sequence: For powering down, starting from ±3.0 V on VCP_FILT± pins, follow the specified sequence.

Alternate Headphone Inputs: Configured using PDN_HP and HP_IN_EN bits. When HP_IN_EN = 1, the internal headphone driver must be disconnected (PDN_HP = 1).

Headphone Presence Detect and Output Load Detection: Supports headphone presence-detect via the HP_DETECT pin, which is debounced to filter brief events.

Headphone Detect Registers: Registers control the headphone-detect debounce and interrupt status.

HP Load Detection: Measures headphone DC load impedance under specific conditions.

AC Load Detection: AC load impedance is measured in the 20 Hz to 20 kHz range.

Clocking Architecture: Requires an MCLK for operation, sourced from a crystal oscillator, external input, or internal RCO.

Clock Output and Fractional-N PLL: Supports clock output through the CLKOUT pin, which can be divided by 2, 3, 4, or 8.

Powering Up and Down the PLL: To power up the PLL, a sequence of enabling and configuring various registers is required.

Filtering Options: Offers selectable filters for digital audio systems, including fast and slow roll-off interpolation filters.

Audio Serial Port (ASP): Configurable for audio data communication, supporting PCM and DoP stream playback.

Clock Generation and Control: Provides flexible clock generation for serial ports, allowing independent clocking.

Audio Serial Port (ASP) Specifications: Outlines the configuration and operation of the Audio Serial Port (ASP) in the CS43130.

Channel Location and Size: Each serial-port channel has a programmable location offset and size.

Frame Start Phase: The frame can start when xSP_LRCK/FSYNC is high or low, depending on the xSP_STP setting.

50/50 Mode: In this mode, the LRCK duty cycle is 50%, and each channel is transferred during one of the two LRCK phases.

Serial Port Status: The ASP has five status bits that indicate various conditions.

DoP (DSD over PCM) Mode: DoP is a protocol for transmitting DSD data over a PCM frame.

DSD Interface: Handles 24-bit samples, with specific bits used for DSD markers.

DSD and PCM Mixing: Allows for mixing PCM notifications during DSD playback.

Standard Interrupts: Uses an interrupt output pin to signal events within its interrupt status registers.

Control Port Operation: Used to access control registers and on-chip memory locations.

Interrupts and Register Bit Fields: Outlines various interrupt events and their corresponding register bit fields and interrupt mask fields.

Control Port Operation: Operates using an I2C interface with the CS43130 acting as a slave device.

Applications: PLL Clocking: The PLL must be turned on if the external system MCLK is not 22.5792 or 24.576 MHz.

Alert Mixing Shutdown: To prevent a DSD mute pattern from turning off the DAC while mixing DSD data with PCM data, the auto mute should be turned off.

Enable/Disable Nonoversampling Filter: Provides sequences to enable or disable the nonoversampling filter.

Enable/Disable Alternate Headphone Path (HPINx): Instructions are provided for enabling and disabling the HPINx path.

Headphone Power Down Sequences: Examples of power down sequences for PCM and DSD are provided.

Headphone Power-Up Initialization: Both PCM and DSD require specific sequences to initialize the headphone output.

Headphone Power-Up Sequence: Involves running initialization, powering up ASP, and ensuring a pop-free startup.

Example Sequences: Startup to I2S Playback: Involves configuring the XTAL driver, enabling interrupts, and setting ASP interface parameters for I2S playback.

Overview: Provides detailed technical instructions for configuring and controlling various audio processing functions in the CS43130 audio codec.

PCM Path Signal Control: Outlines the configuration of PCM Path Signal Control registers to manage volume settings, soft ramp down, and muting conditions.

Headphone Detection: Instructions are provided for enabling headphone detection, configuring debounce times, and setting up interrupts for plug and unplug events.

Class H Amplifier Control: Describes the configuration of the Class H amplifier, including enabling high voltage mode and using internal VCPFILT sources.

Interrupt Management: Detailed steps are provided for enabling and managing various interrupts.

MCLK Frequency Switching: Outlines the procedure for switching the MCLK frequency to accommodate different audio sample rates.

DoP and PCM Mixing: Instructions are provided for mixing DoP and PCM audio streams.

Conclusion: Serves as a comprehensive guide for configuring the CS43130 audio codec.

ASP Channel Configuration: ASP Channel 1 and 2 are configured with a size of 32 bits and are enabled.

PCM Setup and Configuration: PCM is set up with specific filter options, including a high pass filter.

Interrupt and Clock Configuration: ASP interrupts are enabled for overflow, error, late, early, and no LRCK conditions.

Power and Mixing Control: ASP power down control is enabled, and PCM/DoP mixing is configured and enabled.

Headphone Load Measurement: Details the process for measuring both DC and AC impedance of headphone loads.

Disabling Impedance Measurement: The process for disabling the impedance measurement subsystem is outlined.

Register Quick Reference: A quick reference for register addresses and functions is provided.

PLL Settings: Details various PLL settings and configurations.

ASP and XSP Registers: Details various ASP and XSP register settings and configurations.

DSD Registers: Details various DSD register settings and configurations.

Static and Invalid DSD Detection: Static DSD detection is enabled by default.

DSD and PCM Mixing Control: PCM playback path for mixing with DSD can be enabled.

DSD Processor Path Signal Control: Settings include matching DSD stream volume to PCM.

Headphone and PCM Registers: Includes controls for headphone output clamping, PCM filter options, volume control, and signal path adjustments.

Class H Control: Adaptive power adjustment for headphone amplifiers.

HP Detect and Load Measurement: HP detect circuit configuration, debounce timing, and load measurement triggers for AC and DC.

Interrupt Status and Mask Registers: Monitors various conditions such as DAC overflow, HP plug/unplug events, XTAL and PLL readiness, and errors.

PCB Layout Considerations:

Power Supply: Emphasizes the need for clean, independent power supplies for optimal performance.
Grounding: Recommends extensive use of power and ground planes, and proper placement of decoupling capacitors to minimize inductance and unwanted coupling.
HPREFA and HPREFB Routing: Suggests independent routing to ensure interchannel isolation and proper grounding.
QFN Thermal Pad: Advises on proper thermal pad connection to ground for heat dissipation.

Performance Plots: Includes various plots showing passband ripple, stopband attenuation, impulse response, and step response for different filter settings and speeds.

Digital Filter Response: Details various digital filter responses for the CS43130 DAC.

Package Dimensions: Provides detailed dimensions for the 40-Pin QFN and 42-Ball WLCSP packages.

Thermal Characteristics: Thermal resistance parameters are provided for typical JEDEC four-layer boards.

Ordering Information: Lists ordering details for the CS43130 DAC.

Important Notices: Includes legal disclaimers regarding the use of Cirrus Logic products.

Catalog excerpts

CS43130 130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver and Impedance Detection System Features Interrupt Sources Interpolation Filter and Volume Control Interpolation Filter and Volume Control XSP/DSD Audio Interface DSD Processor Popguard® Circuitry Control Port Level Translator FLYC_VCP FLYP_VCP FLYN _VCP VCP_FILT+ VCP_FILT FLYP_VA FLYN_VA -VA Register /Hardware Configuration Copyright  Cirrus Logic, Inc. 2015–2016 (All Rights Reserved) Charge Pump Analog Supply (VA,VCP) Battery Supply +1.8V (VP) Internal Voltage Reference Digital Core FILT+ FILT- Digital LDOs Internal Interface Supply (VL) Supply (VD) +1.8V +1.8V Level Translator • Direct Stream Digital (DSD®) path — Patented DSD processor Enhanced  oversampling DAC architecture – On-chip 50-kHz filter to meet Scarlet Book Super — 32-bit resolution Audio Compact Disk (SACD) recommendations — Up to 384-kHz sampling rate – Matched PCM and DSD analog output levels — Low clock jitter sensitivity – Nondecimating volume control with 0.5-dB step size — Auto mute detection and soft ramp Integrated high performance, ground-centered stereo – DSD and Pulse-code modulation (PCM) mixing for headphone outputs alerts — 130-dB dynamic range (A-weighted) — Dedicated DSD and DoP pin interface — –108-dB total harmonic distortion + noise (THD+N) • Serial audio input path — 110-dB interchannel isolation — Five selectable digital filter responses — Headphone power output – Low-latency mode minimizes pre-echo – 30 mW per channel into 32  – 110 dB of stopband attenuation – 5 mW per channel into 600  — Supports sample rates from 32 to 384 kHz Headphone detection — I2S, right-justified, left-justified, TDM, and — Headphone DC and AC impedance measurement DSD-over-PCM (DoP) interface — Headphone plug-in detection — Master or slave operation — Popguard® technology eliminates pop noise — Volume control with 0.5-dB step size and soft ramp Integrated PLL — 44.1 kHz deemphasis and inverting feature — Support for 11.2896-/22.5792-, 12.288-/24.576-, 9.6-/ • Alternate headphone input 19.2-, 12-/24-, and 13-/26-MHz system MCLK rates • 40-pin QFN or 42-ball CSP package option — Reference clock sourced from XTI/MCLK pin Applications — System clock output • Smart phones, tablets, portable media players, laptops, Mono mode support digital headphones, powered speakers, AVR, home I2C control—up to 1 MHz theater systems, Blu-ray/DVD/SACD p

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CS43130 General Description The CS43130 is a high-performance, 32-bit resolution, stereo audio DAC that supports up to 384-kHz sampling frequency with integrated low-noise ground-centered headphone amplifiers. The advanced 32-bit oversampled multibit modulator with mismatch shaping technology eliminates distortion due to on-chip component mismatch. Proprietary digital-interpolation filters support five selectable filter responses with pseudo-linear phase and ultralow latency to minimize pre-echos and ringing artifacts. Other features include volume control with 0.5-dB steps and digital deemphasis...

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CS43130 Table of Contents 1 Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . 4 1.1 40-Pin QFN (Top-Down, Through-Package View) . . . . . . . . . 4 1.2 42-Ball WLCSP (Top-down, Through-Package View) . . . . . . 5 1.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 Electrostatic Discharge (ESD) Protection Circuitry . . . . . . . . 8 2 Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . 11 Table 3-1. Parameter Definitions...

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CIRRUS LOGIC CS43130 1 Pin Assignments and Descriptions 1 Pin Assignments and Descriptions 1.1 40-Pin QFN (Top-Down, Through-Package View) Q co < a co a RESET INT VP VCP FLYP_VCP FLYC_VCP HP_DETECT VCP_FILT+ Figure 1-1. Top-Down (Through-Package) View—QFN 40-Pin Diagram

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1.2 42-Ball WLCSP (Top-down, Through-Package View) 1.2 42-Ball WLCSP (Top-down, Through-Package View) Charge Pump Power Supplies Figure 1-2. Top-Down (Through-Package) View—42-Ball WLCSP Package

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I.The power supply is determined by ADPT_PWR setting (see Section 4.3.1). VP is used if ADPT_PWR = 001 (VP_LDO Mode) or when necessary for ADPTPWR = 111 (Adapt-to-Signal Mode).

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1.4 Electrostatic Discharge (ESD) Protection Circuitry 1.4 Electrostatic Discharge (ESD) Protection Circuitry ESD-sensitive device. The CS43130 is manufactured on a CMOS process. Therefore, it is generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken while handling and storing this device. This device is qualified to current JEDEC ESD standards. Fig. 1-3 provides a composite view of the ESD domains showing the ESD protection paths between each pad and the substrate (GND), as well as the interrelations between some domains. Note that this figure...

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1.4 Electrostatic Discharge (ESD) Protection Circuitry Table 1-2. ESD Domains (Cont.) ESD Domain VA/–VA Signal Name (See * in Topology Figures for Pad) FLYN_VA FLYP_VA FILT+ FILT– INT VP/VCP_FILT– FLYP_VCP FLYC_VCP HP_DETECT VCP_FILT+/ FLYN_VCP VCP_FILT– HPINA HPINB HPOUTA HPOUTB HPREFA HPREFB VP/GNDCP Domain VCP_FILT+/VCP_FILT– Domain VP/VCP_FILT– Domain

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2 Typical Connection Diagram 2 Typical Connection Diagram VL HPOUTB Headphone Connector HP_DETECT RESET Applications Processor/ MicroController Audio Codec Headphone Output PCM/DoP Digital Audio Source DoP/DSD Digital Audio Source Audio Devices All external passive component values shown are nominal . Clocking Configuration XTAL External MCLK System Clock Key for Capacitor Types Required : * Use low ESR, X7R/X5R capacitors If no type symbol is shown next to a capacitor, any type may be used. ** Use C0G capacitors. VCP_FILT Configuration EXT_VCPFILT = 0 VCP_FILT+ VCP_FILT– GNDCP VCP_FILT+ VCP_FILT–...

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CS43130

CS43130

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