CS42L42
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CS42L42 Low-Power Audio Codec with SoundWire®–I2S/TDM and Audio Processing System Features • Integrated fractional-N PLL — Increases system-clock flexibility for audio processing • Stereo headphone (HP) output with 114-dB dynamic range — Reference clock sourced from either I2S/TDM bit clock — Class H HP amplifier with four-level automatic or or MIPI SoundWire clock manual supply adjust — Power output 2 x 35 mW into 30  • Mono mic input with 114-dB dynamic range — Low-noise headset bias with integrated bias resistor — 1-VRMS input voltage — Integrated AC-coupling capacitors • Integrated detect features — OMTP (Open Mobile Terminal Platform) and AHJ (American headset jack) headset-type detection and configuration with low-impedance internal switches — Mic short (S0 Button) detect with ADC automute — Automatic Hi-Z of headset bias output to ground on headset bias current rise or HP/headset unplug • System wake from headset/headphone plug/unplug or S0 button press • Interrupt output • Mono equalizer for side-tone mix • MIPI® SoundWire® or I2C/I2S/TDM control and audio interface • S/PDIF transmit (Sony/Philips digital interface format) • Audio serial port (ASP) — I2S (two channels) or TDM (up to four channels) — Slave or Hybrid-Master Mode (bit-clock slave and LRCK/FSYNC derived from bit clock) — Sample-rate converter (SRC) for two input channels, with bypass — SRC for one output channel, with bypass — User isochronous audio transport support — Supports up to 192-kHz sample rate to S/PDIF output — Sample rate support for 8 to 192 kHz • Integrated power management — Digital core operates from either an external 1.2-V supply or LDO from a 1.8-V supply. — Step-down charge pump improves HP efficiency — Independent peripheral power-down controls — Standby operation from VP with all other supplies powered off — VP monitor to detect and report brownout conditions — Low-impedance switching suppresses ground-noise Applications • Ultrabooks, tablets, and smartphones • Digital headsets HSIN+ HSIN– Analog Core Step -Down Digital Core Windnoise Filter HPSENSA +VCP_FILT Headset Detect, Switches, and Depletion FET Control Headphone Detect Pseudodifferential Input SWIRE_CLK/ ASP_SCLK SoundWire Audio and Control Port ASP_SDOUT SWIRE_SD/ ASP_LRCK/ SWIRE_SEL ASP_SDIN FSYNC

CS42L42 General Description The CS42L42 is a low-power audio codec with integrated MIPI SoundWire interface or I2C/I2S/TDM interfaces designed for portable applications. It provides a high-dynamic range, stereo DAC for audio playback and a mono high-dynamic-range ADC for audio capture. The CS42L42 provides high performance (up to 24-bit) audio for ADC and DAC audio playback and capture functions as well as for the S/PDIF transmitter. The CS42L42 architecture includes bypassable SRCs and a bypassable, three-band, 32-bit parametric equalizer that allows processing of digital audio data. A...

Table of Contents 1 Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . 4 1.1 WLCSP Pin Out (Through-Package View) . . . . . . . . . . . . . . 4 1.2 QFN Pin Out (Through-Package View) . . . . . . . . . . . . . . . . . 5 1.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 Electrostatic Discharge (ESD) Protection Circuitry . . . . . . . . 8 2 Typical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Electromagnetic Compatibility (EMC) Circuitry . . . . . . . . . . 12 3 Characteristics and...

1 Pin Assignments and Descriptions This section shows pin assignments and describes pin functions. 1.1 WLCSP Pin Out (Through-Package View) ASP_SDIN/ SWIRE_SD ASP_SCLK/ SWIRE_CLK ASP_LRCK/ FSYNC SWIRE_SEL DIGLDO_PDN HSBIAS_ FILT Charge Pump Figure 1-1. WLCSP Pin Diagram (Through-Package View)

CIRRUS LOGIC CS42L42 1.2 QFN Pin Out (Through-Package View) 1.2 QFN Pin Out (Through-Package View) Q CD I LU § CD

I.The power supply is determined by ADPTPWR setting (see Section 7.14.1). VP is used if ADPTPWR = 001 (VP_CP Mode) or when necessary for ADPTPWR = 111 (Adapt-to-Signal Mode)

1.4 Electrostatic Discharge (ESD) Protection Circuitry 1.4 Electrostatic Discharge (ESD) Protection Circuitry ESD-sensitive device. The CS42L42 is manufactured on a CMOS process. Therefore, it is generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken while handling and storing this device. This device is qualified to current JEDEC ESD standards. Fig. 1-3 provides a composite view of the ESD domains showing the ESD protection paths between each pad and the substrate (GNDA) and the interrelations between some domains. Note that this figure...

1.4 Electrostatic Discharge (ESD) Protection Circuitry Table 1-2. ESD Domains (Cont.) ESD Signal Name (CSP/QFN) Domain (See * in Topology Figures for Pad) VCP/ VCP GNDA Substrate (GNDA) GNDHS HS3 HS4 HS_CLAMP1 HS_CLAMP2 HSBIAS_FILT HSBIAS_FILT_REF HSIN+ HSIN– VP VL_SEL INT WAKE RESET DIGLDO_PDN +VCP_ +VCP_FILT FILT/ –VCP_FILT –VCP_ FLYN HPSENSA FILT HPSENSB HPOUTA HPOUTB GNDCP VP/ FLYC –VCP_ FLYP HS3_REF FILT HS4_REF RING_SENSE TIP_SENSE VP/ GNDA VP/GNDA Domain GNDHS +VCP_FILT/–VCP_FILT Domain Substrate (GNDA) Substrate (GNDA) * VP/–VCP_FILT Domain 1.See Section 5.8 for additional...

CIRRUS LOGIC' CS42L42 2 Typical Connections 2 Typical Connections Battery (3.0-5.0 V) WAKE VL_SEL Headphone Output Filter DIGLDO_PDN and VL_SEL Configurations Applications Processor HSIN+ HSIN- DIGLDO_PDN = 0 (GNDD) VL_SEL = 0 (GNDD) VL_SEL DIGLDO_PDN VL VD_FILT All external passive component values shown are nominal TSTI DIGLDO_PDN = 0 (GNDD) VL_SEL = 1 (3.0 to 5.0 V) Battery (VP = 3.0 to 5.0V) VL_SEL DIGLDO_PDN VL DIGLDO_PDN = 1 (3.0 to 5.0 V) VL_SEL = 1 (3.0 to 5.0 V) Battery (VP = 3.0 to 5.0V) Key for Capacitor Types Required * Use low ESR, X7R/X5R capacitors If no type symbol is shown...