• Delta-Sigma Fractional-N Frequency Synthesis: Generates a low jitter 6 - 75 MHz clock from an 8 - 75 MHz reference clock.
• Clock Multiplier/Jitter Reduction: Produces a low jitter 6 - 75 MHz clock from a jittery or intermittent 50 Hz to 30 MHz clock source.
• Highly Accurate PLL Multiplication Factor: Maximum error less than 1 PPM in high-resolution mode.
• I²C/SPI Control Port: Allows for full software control.
• Configurable Auxiliary Output: Supports external oscillators or inexpensive local crystals.
• Minimal Board Space Required: No external analog loop-filter components needed.

The CS2000-CP is a versatile system clocking device utilizing a programmable phase lock loop. It combines a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL, enabling frequency synthesis and low-jitter clock generation from stable or noisy reference clocks. It supports I²C and SPI for software control and is available in commercial and automotive grades.

• Delta-Sigma Fractional-N Frequency Synthesizer: Allows precise frequency synthesis.
• Hybrid Analog-Digital Phase Locked Loop: Combines analog and digital techniques for enhanced performance.

• Timing Reference Clock Input: Supports internal timing reference clock divider and external reference clock.
• Frequency Reference Clock Input: Features CLK_IN skipping mode and adjustable loop bandwidth.
• Output to Input Frequency Ratio Configuration: Offers user-defined ratios and effective ratio configurations.

• SPI and I²C Control: Provides detailed control over device functions and configurations.

• Device I.D. and Revision: Identifies device and revision.
• Device Control: Includes unlock indicator and output disable options.
• Device Configuration: Allows selection of ratio modifiers and auxiliary output sources.

• High Resolution 12.20 Format and High Multiplication 20.12 Format: Provides methods for calculating user-defined ratios.

Details on package dimensions and ordering information are provided for commercial and automotive grades.

The document provides a detailed description of the CS2000-CP1 pin configuration. Key pins include VD for digital power, GND for ground reference, CLK_OUT for PLL clock output, and AUX_OUT for auxiliary output. Other important pins are CLK_IN for frequency reference clock input, XTO/XTI for crystal connections, and control port pins for I²C and SPI modes.

A typical connection diagram is provided, illustrating the necessary components and connections for the CS2000-CP2. It includes resistors for I²C operation, capacitors for power supply stabilization, and connections for low-jitter timing reference systems.

The document outlines recommended operating conditions, absolute maximum ratings, and DC electrical characteristics. Key parameters include power supply voltage, ambient operating temperature, and input/output voltage levels. The document warns against operating beyond specified limits to avoid device damage.

AC characteristics are detailed, including crystal frequency, reference clock input frequency, and PLL clock output frequency. The document specifies conditions for optimal performance, such as clock input pulse width and jitter measurements.

Switching characteristics for I²C and SPI formats are provided, detailing parameters like clock frequency, setup and hold times, and rise/fall times. These specifications ensure proper communication timing between the control port and external devices.

The document outlines the specifications for clock frequency ranges and configurations. The system clock (SysClk) should be between 8 MHz and 14 MHz, while the reference clock (RefClk) should be less than 50 MHz for XTI and 58 MHz for REF_CLK. The document also provides details on the normalized REF_CLK frequency and typical baseband jitter.

1. Crystal Connections (XTI and XTO): An external crystal can be used to generate RefClk by connecting a 20 pF fundamental mode parallel resonant crystal between the XTI and XTO pins.
2. External Reference Clock (REF_CLK): For operation with an external REF_CLK signal, connect XTI/REF_CLK to the reference clock source and leave XTO unconnected or pulled low through a 47 kΩ resistor to GND.
3. Frequency Reference Clock Input (CLK_IN): Used in Hybrid PLL Mode to dynamically generate a fractional-N value for the Frequency Synthesizer.

1. CLK_IN Skipping Mode: Allows the PLL to maintain lock even when the CLK_IN signal has missing pulses for up to 20 ms.
2. Adjusting Minimum Loop Bandwidth: The loop bandwidth of the Digital PLL can be adjusted between 1 Hz and 128 Hz to affect the jitter transfer function.

1. User Defined Ratio (RUD): Determines the input to output clock ratio, stored in a 32-bit format.
2. Ratio Modifier (R-Mod): Used to internally multiply/divide the currently addressed RUD.
3. Effective Ratio (REFF): Calculated as RUD multiplied by RMOD.

1. Ratio modifiers that produce an overflow or truncation of REFF should not be used.
2. The maximum and minimum allowable values for REFF are dictated by the frequency limits for both input and output clocks.

1. Utilize the 12.20 High-Resolution format for RUD when the desired ratio is less than 4096 for better accuracy.
2. Experiment with loop bandwidth settings to avoid system timing errors due to wandering between clocks.

The document includes figures illustrating the external component requirements for crystal circuits, CLK_IN removal scenarios, and the effects of loop bandwidth on clock domains. Table 1 summarizes the available options for the Ratio Modifier (R-Mod).

The document outlines the configuration and control of a device using various registers and control bits. Key sections include the Device Configuration 2 (Address 04h), Ratio Selection (RSel[1:0]), and Lock Clock Ratio (LockClk[1:0]). The Fractional-N Source for Frequency Synthesizer (FracNSrc) is also discussed, highlighting its role in frequency synthesis.

The Ratio Configuration Summary explains the user-defined ratio (RUD) and its storage in registers. The selection between static and dynamic ratio modes is determined by RSel[1:0] or LockClk[1:0] bits. The effective ratio (REFF) is calculated using the user-defined ratio and ratio modifier, corrected for internal dividers. The frequency synthesizer's fractional-N source can be selected manually or automatically.

The PLL clock output pin (CLK_OUT) provides a buffered output from the frequency synthesizer. The output can be set to high-impedance using the ClkOutDis bit. The document also describes conditions under which the PLL output may become unreliable.

The auxiliary output pin (AUX_OUT) can be mapped to various signals, controlled by the AuxOutSrc[1:0] bits. The document details the configuration of the auxiliary output and its potential phase differences from the main PLL clock output.

The document discusses the stability of clock outputs during reconfiguration, noting exceptions that may cause partial clock periods. It also outlines conditions that can cause the PLL to lose lock, affecting the clock signal.

Instructions for powering up the device include applying power, configuring operational settings, and ensuring the EnDevCfg1 and EnDevCfg2 bits are set.

The control port allows configuration via SPI or I²C interfaces. The document provides detailed instructions for both modes, including register access and the importance of maintaining default states for reserved registers.

A quick reference table lists register and bit names with default values, emphasizing the need to set EnDevCfg1 and EnDevCfg2 bits for normal operation.