High Performance, Low Power AVR > ծ 8-Bit Microcontroller > Advanced RISC Architecture120 Powerful Instructions ֖ Most Single Clock Cycle Execution32 x 8 General Purpose Working Registers֖Fully Static Operation > Non-Volatile Program and Data Memories2/4/8K Bytes of In-System Programmable Program Memory Flash?Endurance: 10,000 Write/Erase Cycles֖128/256/512 Bytes of In-System Programmable EEPROM?Endurance: 100,000 Write/Erase Cycles128/256/512 Bytes of Internal SRAM ֖Data retention: 20 years at 85 > C / 100 years at 25 CProgramming Lock for Self-Programming Flash & EEPROM Data Security > Peripheral Features֖One 8-Bit and One 16-Bit Timer/Counter with Two PWM Channels, Each10-bit ADC?8 Single-Ended Channels?12 Differential ADC Channel Pairs with Programmable Gain (1x / 20x)֖Programmable Watchdog Timer with Separate On-chip OscillatorOn-Chip Analog Comparator ֖Universal Serial Interface > Special Microcontroller FeaturesdebugWIRE On-chip Debug System֖In-System Programmable via SPI PortInternal and External Interrupt Sources: Pin Change Interrupt on 12 Pins֖Low Power Idle, ADC Noise Reduction, Standby and Power-Down Modes Enhanced Power-on Reset Circuit֖Programmable Brown-Out Detection CircuitInternal Calibrated Oscillator֖On-Chip Temperature Sensor > I/O and PackagesAvailable in 20-Pin QFN/MLF & 14-Pin SOIC and PDIP֖Twelve Programmable I/O Lines > Industrial Temperature Range: -40 C to +85 C > Low Power ConsumptionActive Mode (1 MHz System Clock): 300 ֵA @ 1.8VPower-down Mode: 0.1 ֵA @ 1.8V > Rev. 8006GAVR֖01/08 size="-1">

Port B also serves the functions of various special features of the ATtiny24/44/84 as listed inSection 10.3 Alternate Port FunctionsӔ on page 57. 1.1.4RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate areset, even if the clock is not running and provided the reset pin has not been disabled. The min-imum pulse length is given in Table 20-4 on page 179. Shorter pulses are not guaranteed togenerate a reset.The reset pin can also be used as a (weak) I/O pin. 1.1.5Port A (PA7...PA0) Port A is a 8-bit bi-directional I/O port with internal pull-up resistors...

The ATtiny24/44/84 provides the following features: 2/4/8K byte of In-System ProgrammableFlash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32general purpose working registers, a 8-bit Timer/Counter with two PWM channels, a 16-bittimer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC,programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmableWatchdog Timer with internal Oscillator, internal calibrated oscillator, and four software select-able power saving modes. Idle mode stops the CPU while...

A comprehensive set of drivers, application notes, data sheets and descriptions on developmenttools are available for download at http://www.atmel.com/avr. > This documentation contains simple code examples that briefly show how to use various parts ofthe device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header filesand interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-tation for more details.For I/O Registers located in the extended...

Data Bus 8-bit > Flash ProgramCounter Statusand Control I/O LinesEEPROM ProgramMemory 32 x 8GeneralPurposeRegistrers > InterruptUnit InstructionDecoder WatchdogTimerAnalogComparator ALU Control Lines > Direct AddressingIndirect Addressing Timer/Counter DataSRAM Timer/Counter 1 UniversalSerial Interface >

The fast-access Register File contains 32 x 8-bit general purpose working registers with a singleclock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-ical ALU operation, two operands are output from the Register File, the operation is executed,and the result is stored back in the Register File in one clock cycle.Six of the 32 registers can be used as three 16-bit indirect address register pointers for DataSpace addressing ֖ enabling efficient address calculations. One of the these address pointerscan also be used as an address pointer for look up tables...

This section describes the general access timing concepts for instruction execution. The AVRCPU is driven by the CPU clock clk > CPU , directly generated from the selected clock source for thechip. No internal clock division is used.Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Har-vard architecture and the fast access Register File concept. This is the basic pipelining conceptto obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 4-4. The Parallel Instruction...

in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) > char cSREG;cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<SREG = cSREG; >

sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) > _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ >

This section describes the different memories in the ATtiny24/44/84. The AVR architecture hastwo main memory spaces, the Data memory and the Program memory space. In addition, theATtiny24/44/84 features an EEPROM Memory for data storage. All three memory spaces are lin-ear and regular. > The ATtiny24/44/84 contains 2/4/8K byte On-chip In-System Reprogrammable Flash memoryfor program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 1024/2048/4096 x 16.The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny24/44/84Program Counter...