Smart Battery AVR ATmega406 Preliminary
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High Performance, Low Power AVR > ծ 8-bit Microcontroller > Advanced RISC Architecture124 Powerful Instructions - Most Single Clock Cycle Execution֖32 x 8 General Purpose Working RegistersFully Static Operation֖Up to 1 MIPS Throughput at 1 MHz > Nonvolatile Program and Data Memories40K Bytes of In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase Cycles֖Optional Boot Code Section with Independent Lock BitsIn-System Programming by On-chip Boot Program True Read-While-Write Operation512 bytes EEPROM, Endurance: 100,000 Write/Erase Cycles֖2K Bytes Internal SRAMProgramming Lock for Software Security > On-chip Debugging֖Extensive On-chip Debug SupportAvailable through JTAG interface > Battery Management Features֖Two, Three, or Four Cells in SeriesDeep Under-voltage Protection֖Over-current Protection (Charge and Discharge)Short-circuit Protection (Discharge) ֖Integrated Cell Balancing FETsHigh Voltage Outputs to Drive Charge/Precharge/Discharge FETs > Peripheral Features֖One 8-bit Timer/Counter with Separate Prescaler, Compare Mode, and PWMOne 16-bit Timer/Counter with Separate Prescaler and Compare Mode֖12-bit Voltage ADC, Eight External and Two Internal ADC InputsHigh Resolution Coulomb Counter ADC for Current Measurements֖TWI Serial Interface for SM-BusProgrammable Wake-up Timer ֖Programmable Watchdog Timer > Special Microcontroller FeaturesPower-on Reset ֖On-chip Voltage RegulatorExternal and Internal Interrupt Sources֖Four Sleep Modes: Idle, Power-save, Power-down, and Power-off > Maximum Withstand Voltage (High-voltage pins): 28V > Temperature Range: -30ְC to 85CЖSpeed Grade: 1 MHz > 2548EAVR֖07/06 size="-1">

PD1..0 PB7..0 XTAL1XTAL2 OscillatorCircuits /ClockGeneration PORTD (2) PORTB (8) OPCOCOD FETControl BatteryProtectionVoltageADC PPI NNIPVT WatchdogOscillator Wake-UpTimer JTAG 8 bit T/C0 CellBalancing PV3PV4 PV2NV WatchdogTimer PV1 DATA BUS Flash SRAM 16 bit T/C1 SGND PowerSupervisionPOR &RESET RESET CPU EEPROM VoltageReference VREFVREFGNDPINI GND VCC CoulumbCounter ADC ChargerDetect VFETVREGBATT VoltageRegulator TWI PORTC (1) PORTA (8) SCL SCA PC0 PA7..0PA3..0 >

The integrated cell balancing FETs allow cell balancing algorithms to be implemented insoftware.The MCU provides the following features: 40K bytes of In-System Programmable Flash withRead-While-Write capabilities, 512 bytes EEPROM, 2K byte SRAM, 32 general purpose workingregisters, 18 general purpose I/O lines, 11 high-voltage I/O lines, a JTAG Interface for On-chipDebugging support and programming, two flexible Timer/Counters with PWM and comparemodes, one Wake-up Timer, an SM-Bus compliant TWI module, internal and external interrupts,a 12-bit Sigma Delta ADC for voltage and temperature...

2.2.1VFET High voltage supply pin. This pin is used as supply for the internal voltage regulator, described inVoltage RegulatorԔ on page 114. In addition the voltage level on this pin is monitored by the bat-tery protection circuit, for deep-under-voltage protection. For details, see Battery ProtectionԔ onpage 125. 2.2.2VCC Digital supply voltage. Normally connected to VREG. 2.2.3VREG Output from the internal Voltage Regulator. Used for external decoupling to ensure stable regu-lator operation. For details, see Voltage RegulatorԔ on page 114. 2.2.4VREF Internal Voltage Reference for...

2.2.10Port C (PC0) Port C is a high voltage Open Drain output port. 2.2.11Port D (PD1:PD0) Port D is a low-voltage 2-bit bi-directional I/O port with internal pull-up resistors (selected foreach bit). As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,even if the clock is not running.Port D also serves the functions of various special features of the ATmega406 as listed in Alter-nate Functions of Port DԔ on page 72. 2.2.12SCL SMBUS clock, Open Drain...

2.2.21XTAL1 Input to the inverting Oscillator amplifier. 2.2.22XTAL2 Output from the inverting Oscillator amplifier. > A comprehensive set of development tools, application notes and datasheets are available fordownload on http://www.atmel.com/avr. > This documentation contains simple code examples that briefly show how to use various parts ofthe device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header filesand interrupt handling in C is compiler dependent. Please...

Data Bus 8-bit > Flash ProgramCounter Statusand Control I/O LinesEEPROM ProgramMemory 32 x 8GeneralPurposeRegistrers > InterruptUnit InstructionDecoder WatchdogTimerI/O Module 2 ALU Control Lines I/O Module1 > Direct AddressingIndirect Addressing DataSRAM I/O Module n >

The fast-access Register File contains 32 x 8-bit general purpose working registers with a singleclock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-ical ALU operation, two operands are output from the Register File, the operation is executed,and the result is stored back in the Register File in one clock cycle.Six of the 32 registers can be used as three 16-bit indirect address register pointers for DataSpace addressing ֖ enabling efficient address calculations. One of the these address pointerscan also be used as an address pointer for look up...

5.5.1The X-register, Y-register, and Z-register The registers R26:R31 have some added functions to their general purpose usage. These regis-ters are 16-bit address pointers for indirect addressing of the data space. The three indirectaddress registers X, Y, and Z are defined as described in Figure 5-3. Figure 5-3. The X-, Y-, and Z-registers In the different addressing modes these address registers have functions as fixed displacement,automatic increment, and automatic decrement (see the AVR Instruction SetԔ description fordetails). > 15XHXL0X-register7070R27 (0x1B)R26...