ATtiny25, ATtiny45, ATtiny85 Automotive
192Pages

High Performance, Low Power AVR > ծ 8-Bit Microcontroller > Advanced RISC ArchitectureՖ120 Powerful Instructions Most Single Clock Cycle Execution֖32 x 8 General Purpose Working RegistersFully Static Operation > Non-volatile Program and Data Memories2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85)֕Endurance: 10,000 Write/Erase Cycles128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85)֕Endurance: 100,000 Write/Erase Cycles128/256/512 Bytes Internal SRAM (ATtiny25/45/85) ֖Programming Lock for Self-Programming Flash Program and EEPROM Data Security > Peripheral FeaturesՖ8-bit Timer/Counter with Prescaler and Two PWM Channels8-bit High Speed Timer/Counter with Separate Prescaler֕2 High Frequency PWM Outputs with Separate Output Compare Registers Programmable Dead Time GeneratorՖUniversal Serial Interface with Start Condition Detector10-bit ADC֕4 Single Ended Channels2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)ՖProgrammable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator > Special Microcontroller FeaturesdebugWIRE On-chip Debug System ֖In-System Programmable via SPI PortExternal and Internal Interrupt Sources֖Low Power Idle, ADC Noise Reduction, and Power-down Modes Enhanced Power-on Reset Circuit֖Programmable Brown-out Detection CircuitInternal Calibrated Oscillator > I/O and PackagesSix Programmable I/O Lines֖8-pin SOIC 20-pin QFN > Low Power ConsumptionActive Mode: ֕1 MHz, 2.7V: 300 AՖPower-down Mode: 0.2 յ A at 2.7V > 7598GAVR֖03/08 size="-1">

2.3.1VCC Supply voltage. 2.3.2GND Ground. 2.3.3Port B (PB5..PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.Port B also serves the functions of various special features of the ATtiny25/45/85 as listed on page 54....

Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. Bit 6 Ֆ T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-nation for the operated bit. A bit from a register in the Register File can be copied...

Figure 4-4. The Parallel Instruction Fetches and Instruction Executions Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destina- tion register. > T1T2T3T4 clk1st Instruction Fetch1st Instruction Execute2nd Instruction Fetch2nd Instruction Execute3rd Instruction Fetch3rd Instruction Execute4th Instruction Fetch CPU Figure 4-5. Single Cycle ALU Operation > T1T2T3T4 clk CPU Total Execution TimeRegister Operands FetchALU Operation ExecuteResult Write Back...

in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) > char cSREG;cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<SREG = cSREG; > sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) > _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ >

4.8.1Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-mum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep...

Figure 5-3. On-chip Data SRAM Access Cycles > clkWRRDDataDataAddress CPU Address validT1T2T3Compute Address ReadWrite Memory Access InstructionNext Instruction The ATtiny25/45/85 contains 128/256/512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For a detailed description of Serial...

Table 5-1. EEPROM Mode Bits > operations. The Programming times for the different modes are shown in Table 5-1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. > EEPM1EEPM0Programming TimeOperation 003.4 msErase and Write in one operation (Atomic Operation)011.8 msErase Only 101.8 msWrite Only11Reserved for future use ֕Bit 3 EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The...

5.3.7Split Byte Programming It is possible to split the erase and write cycle in two different operations. This may be useful if the system requires short access time for some limited period of time (typically if the power sup-ply voltage falls). In order to take advantage of this method, it is required that the locations to be written have been erased before the write operation. But since the erase and write operations are split, it is possible to do the erase operations when the system allows doing time-critical operations (typically after Power-up). 5.3.8Erase To erase a byte, the...