Overview: The Atmel AT86RF215 is a multi-band radio
transceiver designed for sub-1GHz and 2.4GHz bands, suitable for smart metering and applications compliant with IEEE Std 802.15.4g-2012, ETSI TS 102 887-1, and IEEE Std 802.15.4-2015. It features two independent transceivers, each with its own baseband and I/Q data interface, allowing simultaneous operation in both frequency bands.
Specifications: The device supports various frequency bands including European, Chinese, North American, Korean, Japanese, and the worldwide ISM band. It offers a programmable TX output power up to +14.5dBm and a receiver sensitivity down to -123dBm. The transceiver supports multiple PHYs such as MR-FSK, MR-OFDM, MR-O-QPSK, and O-QPSK with various symbol rates and data rates.
Features: Key features include a fully integrated radio transceiver, simultaneous sub-1GHz and 2.4GHz operation, separate RX and TX frame buffers, IEEE MAC support, automatic filter calibration, and a true random number generator. The device is optimized for low BOM cost and ease of production, with low power consumption modes and an industrial temperature range from –40°C to +85°C.
Control and Interfaces: The AT86RF215 is controlled via a fast SPI interface and includes dedicated MAC hardware, a random number generator, and on-board battery monitoring. It can be operated with an external
microcontroller or baseband processor. The device features separate register blocks for sub-1GHz and 2.4GHz radios, with specific naming conventions for registers.
Pin Configuration: The device is housed in a 48-pin low-profile lead-free plastic QFN package. Key pins include differential RF input/output pins for both frequency bands, external and internal supply voltage pins, and SPI interface pins. Proper grounding and decoupling are essential for optimal performance.
Applications: The AT86RF215 is ideal for smart metering and other applications requiring robust wireless communication in various frequency bands, offering high link budget and efficient system integration.
Pin Descriptions and Interfaces: The document details the pin configurations and interfaces, including SPI pins for register access, LVDS I/Q data interface pins, IRQ pin for interrupts, and clock pins for timing signals.
Application Schematic: The AT86RF215 requires a 50Ω differential load for optimal RF performance and operates with a 26MHz TCXO. Decoupling capacitors should be placed close to power supply pins to ensure stability. A low-pass filter is recommended for the CLKO pin to reduce signal harmonics.
Control and Data Interfaces: The document describes reset modes, SPI control interface, interrupt signaling, and clock output configuration, emphasizing the importance of proper configuration for optimal performance.
Clock Output Configuration: The clock output signal is configurable via the RF_CLKO register, with options for driver strength and frequency settings. The clock signal is paused in DEEP_SLEEP state and resumes with previous settings upon waking.
Serial I/Q Data Interface: The AT86RF215 uses a low voltage differential signaling (LVDS) interface for data transfer with an external baseband processor, supporting a data rate of 128Mb/s with a 64MHz clock frequency.
Configuration and Characteristics: The document details the configuration of I/Q data interface registers, including settings for driver strength, voltage swing, and synchronization parameters.
Operating Modes: The AT86RF215 supports two operating modes for its transceivers: Baseband mode and I/Q radio mode, with specific configurations for each mode.
State Machine: The state machine governs transceiver operations, with states including TRXOFF, SLEEP, DEEP_SLEEP, TXPREP, and TX. Transitions between states are controlled by commands and can trigger interrupts.
Power Management: Power states include SLEEP and DEEP_SLEEP, with DEEP_SLEEP offering the lowest power consumption. Wake-up procedures are detailed for transitioning back to active states.
Transceiver States and Commands: The document describes the operation of the Atmel AT86RF215 transceiver, focusing on its states and commands, including state transitions and interrupt management.
Signal Processing Flow: The document describes the signal processing flow for the Atmel AT86RF215, focusing on the up-sampling and filtering stages, with configurable cut-off frequencies and up-sampling stages.
Transmit Processing Delay: The processing delay is dependent on the settings of TXDFE.RCUT and TXDFE.SR, with detailed values provided in Table 6-1.
Transmitter Analog Frontend: The transmitter uses a direct up-conversion architecture, with post-DAC signals passing through 2nd order low-pass filters.
Power Amplifier: The power amplifier's ramp time is adjustable to control spurious emissions, with adjustable TX power in 1dB steps.
Transmit Control: Three methods are available: Baseband mode, I/Q radio mode with SPI control, and I/Q radio mode using embedded control.
Receiver Frontend: The receiver frontend configuration requires the transceiver to be in the TRXOFF state, with a
low-noise amplifier and variable IF with band-pass filtering.
Receiver Digital Frontend: The Receiver Digital Frontend (RX_DFE) is responsible for converting the complex baseband signal at the I/Q ADC interface through discrete time sampling rate conversion.
Automatic Gain Control (AGC): The AGC is a discrete time regulation loop that adjusts the gain of the Low Noise Amplifier (LNA) to minimize control deviation.
Energy Measurement: The energy measurement module is used for channel selection and clear channel assessment, with a wide measurement range and 1dB resolution.
Frequency Settings: The document outlines various frequency settings for the transceiver, including specific frequency values and their corresponding hexadecimal codes.
Receiver AGC Control (RFn_AGCC): This section describes the AGC control register, detailing each bit's function.
Receiver AGCG (RFn_AGCS): This register manages the AGC target level and receiver gain.
Received Signal Strength Indicator (RFn_RSSI): The RSSI register provides the received signal strength in dBm.
Energy Detection Configuration (RFn_EDC): This section explains the energy detection modes, including automatic, single, continuous, and disabled modes.
Frequency Synthesizer (PLL): The synthesizer generates RF frequencies for transmission and reception, with two separate synthesizers for sub-1GHz and 2.4GHz transceivers.
Channel Configuration: The channel frequency must be configured in specific states using various registers.
Crystal Oscillator and TCXO: The AT86RF215 features a crystal oscillator that can operate with an external crystal or TCXO, generating a 26MHz clock with low phase noise.
Frontend Control: The device provides four output pins for controlling external frontends, such as LNA and PA, with configurations for automatic gain control.
Voltage Regulators: The document outlines the status of voltage regulators in various transceiver states, emphasizing that DVDD, AVDD0, and AVDD1 must not be shorted.
Battery Monitor: The battery monitor detects low supply voltage at pin EVDD, with configurable voltage thresholds.
Analog Calibrations: Calibration loops are initiated during state transitions to minimize performance degradation.
Baseband Core: The AT86RF215 features baseband core functionality for MR-FSK, MR-OFDM, and O-QPSK PHYs.
Baseband Interrupts and Receive Process: The document describes the baseband interrupts during frame reception, highlighting the conditions under which a frame reception is canceled.
MR-FSK PHY Overview: The AT86RF215 implements MR-FSK mode as per IEEE Std 802.15.4g-2012, with features like dual synchronization word detection and forward error correction.
Coding and Modulation: The document explains the coding and modulation processes, including FEC schemes, data whitening, and bit-to-symbol mapping for 2-level and 4-level FSK.
PPDU Types: The structure of PPDUs is based on IEEE Std 802.15.4g-2012, with various types like SFD-16 and RAW-SFD-16.
Transmit Operation and Configuration: The document provides guidelines for configuring the transmitter, including recommended settings for modulation index and symbol rates.
IEEE Mode: For PPDUs without mode switch, the PHR sub-fields must be configured according to specific standards.
RAW Mode Configuration and Transmission: The document outlines the configuration and transmission of a PPDU with mode switch using RAW mode.
Receive Operation and Configuration: The document details the general receive configuration, emphasizing the importance of setting the AT86RF215 to state TRXOFF during configuration.
Preamble and Synchronization Word Detection: The preamble detection process involves the receiver being in a LISTEN state and transitioning to PREAMBLE_LOCK upon detecting a preamble pattern.
IEEE Mode and RAW Mode Reception: The document distinguishes between PPDU reception with and without mode switch.
Receiver Override and Reduced Power Consumption: Receiver override is supported to mitigate capture effects, with specific threshold configurations.
Gaussian Frequency Shift Keying (GFSK): The document describes the phase of the ideal continuous-phase baseband signal using GFSK, defined by a mathematical equation involving the discrete-time frequency symbol sequence, symbol rate, and modulation index.
SFD-Correlation: Synchronization word detection is based on correlating expected synchronization words with binary frequency estimates from the demodulator.
Register Descriptions: The document provides detailed descriptions of various registers used for configuring the FSK PHY.
FSK Preemphasis Configuration: The document outlines the configuration of FSK Preemphasis registers, FSKPE1 and FSKPE2, which are used for direct modulation preemphasis in FSK systems.
Transmitter TX Digital Frontend: The RFn_TXDFE register configures the transmitter digital frontend.
FSK Reduced Power Consumption: The BBCn_FSKRPC register manages reduced power consumption for MR-FSK PHY.
MR-OFDM PHY Overview: The MR-OFDM PHY supports data rates from 50kb/s to 2400kb/s, with modulation schemes including BPSK, QPSK, and 16-QAM.
Transmitter Configuration: Configuration steps for the MR-OFDM transmitter include activating the physical layer, setting bandwidth options, and configuring modulation and coding schemes.
Receiver Configuration: The receiver configuration involves setting bandwidth options, configuring interleaving, and adjusting AGC settings.
Register Descriptions: The document provides detailed descriptions of various registers, including BBCn_OFDMPHRTX for transmitter PHY header configuration and BBCn_OFDMPHRRX for receiver PHY header status.
MR-OFDM PHY Configuration: The document details the configuration of MR-OFDM PHY, including spurious compensation, modulation and coding scheme, and bandwidth options.
O-QPSK PHY Overview: The document describes the O-QPSK PHY, supporting MR-O-QPSK and legacy O-QPSK PHY types according to IEEE Std 802.15.4g-2012 and ETSI TS 102 887-1.
Transmit Operation and Configuration: The document provides guidelines for configuring the transmitter, including chip rate selection and pulse shaping filter configuration.
Receive Operation and Configuration: The document details the configuration of receiver units for MR-O-QPSK and legacy O-QPSK frames.
AGC Settings and Receiver Override: The document outlines the Automatic Gain Control (AGC) settings for different chip rates and the support for receiver override (RXO) to mitigate capture effects.
Crystal Tolerance and Frequency Bands: The document discusses combining O-QPSK modes with various center frequencies, emphasizing constraints on maximum crystal tolerance.
Spurious Emission and Power Consumption: At certain center frequencies, spurious emissions may occur, and spurious compensation can be enabled.
Frame Buffer Management: The AT86RF215 has separate frame buffers for TX and RX, accessible via SPI.
Frame Transmit Flow: The document describes a reliable frame transmit flow where the frame payload is stored in the transmit frame buffer before transmission starts.
Frame Buffer Level Monitor: This monitor tracks the number of octets read/stored in the frame buffer.
Frame Buffer Level Interrupt: This interrupt is triggered when the number of received bytes exceeds a configured value.
Frame Check Sequence (FCS): The AT86RF215 supports automatic FCS handling for both transmission and reception.
IEEE MAC Support: The device provides embedded IEEE MAC support, including frame filtering to discard irrelevant frames.
Frame Filter: The frame filter evaluates received frames against predefined criteria, such as address information and frame types.
Frame Filtering: The chip uses a multi-stage filtering process to determine if incoming frames should be accepted.
Multi Address Filtering (MAF): The device can handle multiple network addresses using four independent third-level filter units.
Automatic Acknowledgement (AACK): This feature automatically sends an ACK frame if certain conditions are met.
Transmit and Switch to Receive (TX2RX): This procedure allows the device to switch to receive mode automatically after transmitting a frame.
Clear Channel Assessment with Automatic Transmit (CCATX): CCATX assesses channel availability using energy detection.
Promiscuous Mode (PM): This mode is controlled by the AFC0.PM sub-register, allowing the device to receive all frames regardless of address filtering.
Address Filter Configuration (AFC): The AFC0 and AFC1 registers manage address filtering.
Frame Type and Version Masks: The AFFTM and AFFVM registers control which frame types and versions are processed or discarded.
Address Filter Status (AFS): This register indicates the status of address matches and extended matches.
MAC Extended Address: Registers BBCn_MACEA0 to BBCn_MACEA7 store the MAC extended address across multiple bytes.
MAC Pan ID and Short Address Filters: Registers like BBCn_MACPID0F0 and BBCn_MACSHA0F0 store the MAC Pan ID and short address for different filter units.
Auto Mode Configuration and Status (AMCS): This register manages automatic acknowledgment features.
Automatic Acknowledge (AACK) Configuration: AACK can be enabled or disabled using sub-register values.
CCA Energy Detection (CCAED): Indicates the status of the last CCA measurement.
CCA Measurement and Automatic Transmit (CCATX): Enables or disables the CCATX procedure.
Transmit and Switch to Receive (TX2RX): Automatically switches the transceiver to receive state after a transmit is completed.
Auto Mode Energy Detection Threshold (BBCn_AMEDT): Contains the energy detection threshold for CCA measurement.
Auto Mode Automatic ACK Pending Data (BBCn_AMAACKPD): Configures the behavior of the pending data bit in an automatic acknowledgement frame.
Auto Mode Automatic ACK Time (BBCn_AMAACKTL and BBCn_AMAACKTH): Configures the time between IRQ RXFE and an automatic acknowledgement frame start.
Random Number Generator: Generates random values by observing noise, available in register RFn_RNDV.
Phase Measurement Unit (PMU): Monitors phase and other signal parameters of the RX_DFE output.
Timestamp Counter: Contains a 32-bit counter for capturing timestamp information of received or transmitted frames.
Counter Configuration: The document describes the configuration of a 32-bit timestamp counter with a resolution of 1/32MHz.
Transceiver Usage: The AT86RF215 transceiver can be configured for transmit and receive operations in baseband mode.
Example Configuration: An example configuration for operating the transceiver in the 915MHz band using MR-OFDM Option 1 is provided.
Transmit and Receive Procedures: The document outlines procedures for transmitting and receiving frames using both basic and auto modes.
Transmit Procedure Using Auto Mode: The document outlines the use of auto mode for transmitting frames, which combines Clear Channel Assessment (CCA) and frame transmission to minimize microcontroller interaction.
Receive Procedure Using Auto Mode: The receive procedure involves automatic acknowledgment transmission (AACK) using a frame filter module.
Transmitter Usage in I/Q Radio Mode: Configuration for I/Q radio mode transmission involves enabling I/Q mode, setting up transmitter analog and digital frontends, and configuring channel parameters.
Receiver Usage in I/Q Radio Mode: For I/Q radio mode reception, the document describes enabling I/Q mode, configuring receiver frontends, and setting AGC registers.
Register Summary: A summary of registers is provided, indicating reserved bits and their reset values.
Specifications: The Atmel AT86RF215 is a wireless transceiver designed for low-rate wireless personal area networks (LR-WPANs).
Ordering Information: The device is available in various configurations, including tray and tape & reel packaging.
Errata Overview: The document lists several errata for different versions of the AT86RF215, AT86RF215M, and AT86RF215IQ devices.
Errata Details: The document provides detailed descriptions of known issues and workarounds for the AT86RF215.
References: The document references several IEEE standards and ETSI specifications relevant to wireless communication and device compatibility.
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