The AVR core combines a rich instruction set with 32 general purpose working registers. All the32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independentregisters to be accessed in one single instruction executed in one clock cycle. The resultingarchitecture is more code efficient while achieving throughputs up to ten times faster than con-ventional CISC microcontrollers.The ATmega329/3290/649/6490 provides the following features: 32/64K bytes of In-SystemProgrammable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte SRAM, 54/69 general...

The ATmega329, ATmega3290, ATmega649, and ATmega6490 differs only in memory sizes,pin count and pinout. Table 3-1 on page 6 summarizes the different configurations for the fourdevices. Table 3-1. Configuration Summary > DeviceFlashEEPROMRAMLCD SegmentsGeneral PurposeI/O Pins ATmega32932K bytes1K bytes2K bytes4 x 2554ATmega329032K bytes1K bytes2K bytes4 x 4069ATmega64964K bytes2K bytes4K bytes4 x 2554ATmega649064K bytes2K bytes4K bytes4 x 4069 The following section describes the I/O-pin special functions. 3.3.1V > CC Digital supply voltage. 3.3.2GND Ground. 3.3.3Port A (PA7..PA0) Port A is an...

3.3.5Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort C output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port C pins that are externally pulled low will source current if the pull-upresistors are activated. The Port C pins are tri-stated when a reset condition becomes active,even if the clock is not running.Port C also serves the functions of special features of the ATmega329/3290/649/6490 as listedon page 71. 3.3.6Port D (PD7..PD0) Port D is an 8-bit bi-directional...

3.3.9Port G (PG5..PG0) Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort G output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port G pins that are externally pulled low will source current if the pull-upresistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.Port G also serves the functions of various special features of the ATmega329/3290/649/6490as listed on page 75. 3.3.10Port H (PH7..PH0) Port H is a 8-bit...

3.3.17LCDCAP An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Fig-ure 24-2. This capacitor acts as a reservoir for LCD power (V > LCD ). A large capacitance reducesripple on V > LCD but increases the time until V > LCD reaches its target value. > A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. > Note:1. Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25аC. > This documentation...

The fast-access Register File contains 32 x 8-bit general purpose working registers with a singleclock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-ical ALU operation, two operands are output from the Register File, the operation is executed,and the result is stored back in the Register File in one clock cycle.Six of the 32 registers can be used as three 16-bit indirect address register pointers for DataSpace addressing ֖ enabling efficient address calculations. One of the these address pointerscan also be used as an address pointer for look up tables...

This section describes the general access timing concepts for instruction execution. The AVRCPU is driven by the CPU clock clk > CPU , directly generated from the selected clock source for thechip. No internal clock division is used.Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Har-vard architecture and the fast-access Register File concept. This is the basic pipelining conceptto obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 7-4. The Parallel Instruction...

in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) > char cSREG;cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<

sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) > __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ >

This section describes the different memories in the ATmega329/3290/649/6490. The AVRarchitecture has two main memory spaces, the Data Memory and the Program Memory space.In addition, the ATmega329/3290/649/6490 features an EEPROM Memory for data storage. Allthree memory spaces are linear. > The ATmega329/3290/649/6490 contains 32/64K bytes On-chip In-System ReprogrammableFlash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flashis organized as 16/32K x 16. For software security, the Flash Program memory space is dividedinto two sections, Boot Program section...

Figure 8-2 shows how the ATmega329/3290/649/6490 SRAM Memory is organized.The ATmega329/3290/649/6490 is a complex microcontroller with more peripheral units thancan be supported within the 64 locations reserved in the Opcode for the IN and OUT instruc-tions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD andLD/LDS/LDD instructions can be used. The lower 2304/4352 data memory locations address both the Register File, the I/O memory,Extended I/O memory, and the internal data SRAM. The first 32 locations address the RegisterFile, the next 64 location the standard I/O memory,...