High-performance, Low-power AVR > ծ 8-bit Microcontroller > Advanced RISC Architecture131 Powerful Instructions ֖ Most Single-clock Cycle Execution32 x 8 General Purpose Working Registers֖Fully Static Operation Up to 20 MIPS Throughput at 20 MHz֖On-chip 2-cycle Multiplier > High Endurance Non-volatile Memory segments16/32/64K Bytes of In-System Self-programmable Flash program memory֖512B/1K/2K Bytes EEPROM1/2/4K Bytes Internal SRAM֖Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM Data retention: 20 years at 85 C/100 years at 25 C֖Optional Boot Code Section with Independent Lock BitsIn-System Programming by On-chip Boot ProgramTrue Read-While-Write OperationProgramming Lock for Software Security > JTAG (IEEE std. 1149.1 Compliant) Interface֖Boundary-scan Capabilities According to the JTAG StandardExtensive On-chip Debug Support֖Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface > Peripheral FeaturesTwo 8-bit Timer/Counters with Separate Prescalers and Compare Modes֖One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture ModeReal Time Counter with Separate Oscillator ֖Six PWM Channels8-channel, 10-bit ADCDifferential mode with selectable gain at 1x, 10x or 200x֖Byte-oriented Two-wire Serial Interface Two Programmable Serial USART֖Master/Slave SPI Serial InterfaceProgrammable Watchdog Timer with Separate On-chip Oscillator ֖On-chip Analog ComparatorInterrupt and Wake-up on Pin Change > Special Microcontroller Features֖Power-on Reset and Programmable Brown-out DetectionInternal Calibrated RC Oscillator֖External and Internal Interrupt Sources Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby > I/O and Packages֖32 Programmable I/O Lines40-pin PDIP, 44-lead TQFP, 44-pad QFN/MLF (ATmega164P/324P/644P) > Power Consumption at 1 MHz, 1.8V, 25 C for ATmega164P/324P/644PActive: 0.4 mA֖Power-down Mode: 0.1AՖPower-save Mode: 0.6A (Including 32 kHz RTC) > 8011IՖAVR05/08 size="-1">

PA7..0 PB7..0 > PowerSupervisionPOR / BOD &RESET RESET PORT A (8) PORT B (8) > WatchdogTimer GND VCC WatchdogOscillator A/DConverter USART 0 > XTAL1XTAL2 OscillatorCircuits /ClockGeneration Internal Bandgap referenceAnalogComparator EEPROM SPI 8bit T/C 0 > CPU JTAG/OCD 16bit T/C 1 USART 1 TWI FLASH SRAM 8bit T/C 2 PORT C (8) PORT D (8) TOSC1/PC6TOSC2/PC7 PC5..0 PD7..0 >

The ATmega164P/324P/644P provides the following features: 16/32/64K bytes of In-SystemProgrammable Flash with Read-While-Write capabilities, 512B/1K/2K bytes EEPROM, 1/2/4Kbytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real TimeCounter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byteoriented 2-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stagewith programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serialport, IEEE std. 1149.1 compliant JTAG test interface, also used...

2.3.1VCC Digital supply voltage. 2.3.2GND Ground. 2.3.3Port A (PA7:PA0) Port A serves as analog inputs to the Analog-to-digital Converter.Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected foreach bit). The Port A output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port A pins that are externally pulled low will source current ifthe pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomesactive, even if the clock is not running.Port A also serves the functions...

2.3.7RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate areset, even if the clock is not running. The minimum pulse length is given in System and ResetCharacteristicsԔ on page 332. Shorter pulses are not guaranteed to generate a reset. 2.3.8XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.9XTAL2 Output from the inverting Oscillator amplifier. 2.3.10AVCC AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be exter-nally connected to V > CC , even if the ADC...

A comprehensive set of development tools, application notes and datasheetsare available fordownload on http://www.atmel.com/avr. 8 >

This documentation contains simple code examples that briefly show how to use various parts ofthe device. Be aware that not all C compiler vendors include bit definitions in the header filesand interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-tation for more details.The code examples assume that the part specific header file is included before compilation. ForI/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instruc-tions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and"STS"...

ical ALU operation, two operands are output from the Register File, the operation is executed,and the result is stored back in the Register File in one clock cycle.Six of the 32 registers can be used as three 16-bit indirect address register pointers for DataSpace addressing ֖ enabling efficient address calculations. One of the these address pointerscan also be used as an address pointer for look up tables in Flash program memory. Theseadded function registers are the 16-bit X-, Y-, and Z-register, described later in this section.The ALU supports arithmetic and logic operations between registers...

T1T2T3T4 clk1st Instruction Fetch1st Instruction Execute2nd Instruction Fetch > CPU 2 nd Instruction Execute3rd Instruction Fetch3rd Instruction Execute4th Instruction Fetch > T1T2T3T4 clk > CPU Total Execution Time R egister Operands FetchALU Operation ExecuteResult Write Back >

in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) > char cSREG;cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<