ATmega1284P Preliminary
356Pages

High-performance, Low-power AVR > ծ 8-bit Microcontroller > Advanced RISC ArchitectureՖ131 Powerful Instructions Most Single-clock Cycle Execution֖32 x 8 General Purpose Working Registers Fully Static Operation֖Up to 20 MIPS Throughput at 20 MHzOn-chip 2-cycle Multiplier > Nonvolatile Program and Data Memories128K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles֖Optional Boot Code Section with Independent Lock BitsIn-System Programming by On-chip Boot Program True Read-While-Write Operation4K Bytes EEPROMEndurance: 100,000 Write/Erase Cycles֖16K Bytes Internal SRAMProgramming Lock for Software Security > JTAG (IEEE std. 1149.1 Compliant) InterfaceBoundary-scan Capabilities According to the JTAG Standard֖Extensive On-chip Debug SupportProgramming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface > Peripheral FeaturesTwo 8-bit Timer/Counters with Separate Prescalers and Compare Modes֖Two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture ModeReal Time Counter with Separate Oscillator֖Six PWM Channels 8-channel, 10-bit ADCDifferential mode with selectable gain at 1x, 10x or 200x֖Byte-oriented Two-wire Serial Interface Two Programmable Serial USART֖Master/Slave SPI Serial InterfaceProgrammable Watchdog Timer with Separate On-chip Oscillator֖On-chip Analog ComparatorInterrupt and Wake-up on Pin Change > Special Microcontroller FeaturesPower-on Reset and Programmable Brown-out Detection֖Internal Calibrated RC OscillatorExternal and Internal Interrupt Sources ֖Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby > I/O and PackagesՖ32 Programmable I/O Lines40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF > Power Consumption at 1 MHz, 1.8V, 25 CActive: TBD ֵAPower-down Mode: TBD ֵAPower-save Mode: TBD ֵA (Including 32 kHz RTC) > 8059BAVR֖05/08 size="-1">

The ATmega1284P provides the following features: 128K bytes of In-System ProgrammableFlash with Read-While-Write capabilities, 4K bytes EEPROM, 16K bytes SRAM, 32 general pur-pose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexibleTimer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Inter-face, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain,programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1compliant JTAG test interface, also used for accessing the...

2.2.4Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort B output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port B pins that are externally pulled low will source current if the pull-upresistors are activated. The Port B pins are tri-stated when a reset condition becomes active,even if the clock is not running.Port B also serves the functions of various special features of the ATmega1284P as listed onpage 81. 2.2.5Port C (PC7:PC0) Port C is an 8-bit...

A comprehensive set of development tools, application notes and datasheetsare available fordownload on http://www.atmel.com/avr. 6 >

This documentation contains simple code examples that briefly show how to use various parts ofthe device. Be aware that not all C compiler vendors include bit definitions in the header filesand interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-tation for more details.The code examples assume that the part specific header file is included before compilation. ForI/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instruc-tions must be replaced with instructions that allow access to extended I/O. Typically "LDS"...

ical ALU operation, two operands are output from the Register File, the operation is executed,and the result is stored back in the Register File in one clock cycle.Six of the 32 registers can be used as three 16-bit indirect address register pointers for DataSpace addressing ֖ enabling efficient address calculations. One of the these address pointerscan also be used as an address pointer for look up tables in Flash program memory. Theseadded function registers are the 16-bit X-, Y-, and Z-register, described later in this section.The ALU supports arithmetic and logic operations between...

Figure 5-5. The Parallel Instruction Fetches and Instruction Executions Figure 5-6 shows the internal timing concept for the Register File. In a single clock cycle an ALUoperation using two register operands is executed, and the result is stored back to the destina- tion register. > T1T2T3T4 clk1st Instruction Fetch1st Instruction Execute2nd Instruction Fetch2nd Instruction Execute3rd Instruction Fetch3rd Instruction Execute4th Instruction Fetch CPU Figure 5-6. Single Cycle ALU Operation > T1T2T3T4 clk CPU Total Execution TimeRegister Operands FetchALU Operation ExecuteResult Write Back The...

in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) > char cSREG;cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<

sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) > __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ >

This section describes the different memories in the ATmega1284P. The AVR architecture hastwo main memory spaces, the Data Memory and the Program Memory space. In addition, theATmega1284P features an EEPROM Memory for data storage. All three memory spaces are lin- ear and regular. > The ATmega1284P contains 128K bytes On-chip In-System Reprogrammable Flash memory forprogram storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as64x16. For software security, the Flash Program memory space is divided into two sections,Boot Program section and Application Program...