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Atmel
ATA6616C/ATA6617C LIN SiP (System-in-Package) Solution Including LIN Transceiver, 5V/50 mA Voltage Regulator, Window Watchdog and AVR ATtiny87 (ATtiny167) Automotive Microcontroller with 8K (16K) Flash Memory

ATA6616C/ATA6617C LIN SiP (System-in-Package) Solution Including LIN Transceiver, 5V/50 mA Voltage Regulator, Window Watchdog and AVR ATtiny87 (ATtiny167) Automotive Microcontroller with 8K (16K) Flash Memory

Product catalog summary

General Features
The ATA6616C/ATA6617C is a high-performance, low-power AVR 8-bit microcontroller with an integrated LIN transceiver, 5V regulator, and watchdog. It features low current consumption in sleep mode, 8K/16K flash memory, supports up to 40V supply voltage, and operates from -40°C to +125°C. It is available in a QFN38 package.

Description
This System-in-Package (SiP) is designed for LIN-bus node applications, combining a LIN-system-basis-chip (LIN-SBC) ATA6624 and an AVR microcontroller (ATtiny87/ATtiny167), offering flexibility similar to discrete components.

Pin Configuration
Detailed pin descriptions for the QFN38 package are provided, including functions for I/O lines, voltage regulator inputs/outputs, and LIN bus line input/output.

Absolute Maximum Ratings
Maximum ratings for the SiP, LIN-SBC, and microcontroller are outlined, including ESD ratings, storage and operating temperatures, and voltage/current limits. Exceeding these ratings may cause permanent damage.

LIN System-basis-chip Block
The LIN-SBC supports master and slave operations, with a supply voltage up to 40V and a low-drop voltage regulator with 85mA current capability. It features various modes, wake-up capabilities, and complies with LIN 2.0, 2.1, and SAEJ2602-2 specifications.

Functional Description
Details on physical layer compatibility, supply pin operations, voltage regulator functions, and bus pin characteristics are provided. It describes the functionality of various input/output pins, highlighting their roles in device operation and mode control.

Modes of Operation
The device operates in several modes: Normal, Silent, Sleep, Fail-safe, and Unpowered, each with specific characteristics regarding VCC, communication, and watchdog status.

Voltage Regulator
Requires external capacitors for stability, with recommendations for capacitor values based on application needs.

Watchdog
Monitors the microcontroller's trigger signals and generates a reset if not received within a specified time window. The timing is adjustable via an external resistor.

Microcontroller Features
The Atmel ATtiny87/ATtiny167 microcontroller features a high-performance, low-power AVR 8-bit architecture with 123 instructions, 8K/16K bytes of flash memory, and various peripheral features including LIN/UART controllers, timers, SPI interfaces, and a 10-bit ADC.

Specifications
Details on ADC channel pairs, on-chip analog comparator, current source for LIN node identification, on-chip temperature sensor, and programmable watchdog timer are provided. It highlights special features like dynamic clock switching and hardware in-system programmable via SPI Port.

Procedures
The architecture of the AVR CPU core is outlined, emphasizing its Harvard architecture with separate memories and buses for program and data.

Norms and Standards
The microcontrollers are developed according to ISO-TS-16949 standards and meet AEC-Q100 grade 1 automotive quality requirements.

Recommendations
Use the comprehensive set of development tools, application notes, and datasheets available on the Atmel website for optimal utilization of the microcontrollers.

Key Data from Tables and Diagrams
The memory size summary table compares the ATtiny87 and ATtiny167, highlighting differences in flash memory size. Block diagrams illustrate the architecture of the AVR CPU and the general-purpose working registers.

Critical Information
The microcontrollers' ability to execute powerful instructions in a single clock cycle is emphasized, achieving high throughput and optimizing power consumption.

Stack Pointer and Memory Management
The stack pointer in AVR microcontrollers points to the data SRAM stack area, which must be defined before executing subroutine calls or enabling interrupts.

Instruction Execution Timing
The AVR CPU uses a Harvard architecture for parallel instruction fetches and executions, achieving up to 1 MIPS per MHz.

Reset and Interrupt Handling
AVR microcontrollers have multiple interrupt sources, each with a separate program vector. Interrupts are prioritized by their vector address.

AVR Memories
The Atmel ATtiny87/167 features three main memory spaces: data memory, program memory, and EEPROM.

EEPROM Operations
Before writing to EEPROM, ensure previous data is erased. During programming, no other EEPROM operations can be performed.

Code Examples
Assembly and C code examples are provided for EEPROM write and read operations.

Preventing EEPROM Corruption
Low VCC can cause EEPROM data corruption. Keep AVR RESET active during low power supply periods to prevent corruption.

I/O Memory
Atmel ATtiny87/167 I/Os and peripherals are in the I/O space.

EEPROM Registers
EEARH and EEARL specify EEPROM address. EEDR contains data for write/read operations.

System Clock and Clock Options
ATtiny87/167 offers internal and external clock sources. Clock switching should be managed carefully to avoid incorrect configurations.

Calibrated Internal RC Oscillator
The internal RC oscillator provides an approximate 8.0MHz clock, nominal at 5V and 25°C.

128kHz Internal Oscillator
This low power oscillator provides a 128kHz clock, nominal at 5V and 25°C.

Crystal Oscillator
The crystal oscillator can use either a quartz crystal or a ceramic resonator.

Low-frequency Crystal Oscillator
This oscillator uses a 32.768kHz watch crystal as the clock source.

External Clock
The device can be driven by an external clock source.

Clock Output Buffer
If not using a crystal oscillator, the system clock can be output on the CLKO pin.

Dynamic Clock Switch
The device features a dynamic clock switch circuit allowing clocks to be turned on and off on the fly.

CLKSELR Register
At reset, bits of the Low Fuse Byte are copied into the CLKSELR register.

Enable/Disable Clock Source
Commands are available to enable or disable clock sources.

Clock Switching
The system clock can be switched between various sources.

Clock Source Switching Procedure
The document outlines the procedure for switching clock sources in the Atmel ATtiny87/167 microcontroller.

Clock Monitoring
Clock monitoring is essential for system safety, covering both peripheral and system clock sources.

System Clock Prescaler
The system clock can be divided using the Clock Prescaler Register (CLKPR) to reduce power consumption.

Register Descriptions

OSCCAL – Oscillator Calibration Register: Used to trim the internal RC oscillator frequency.
CLKPR – Clock Prescaler Register: Allows runtime adjustment of clock frequency.
CLKCSR – Clock Control and Status Register: Manages clock control commands and status.
CLKSELR – Clock Selection Register: Manages clock source selection and start-up times.

Power Management and Sleep Modes
Sleep modes allow the shutdown of unused MCU modules to save power.

Sleep Modes Overview
The Atmel ATtiny87/167 microcontroller offers four sleep modes: Idle, ADC Noise Reduction, Power-down, and Power-save.

Sleep Mode Descriptions

Idle Mode: Stops the CPU while allowing other peripherals like SPI and ADC to operate.
ADC Noise Reduction Mode: Halts most clocks except those necessary for ADC operations.
Power-down Mode: Stops all clocks, allowing only asynchronous modules to operate.
Power-save Mode: Similar to Power-down but allows Timer/Counter0 to run if clocked asynchronously.

BOD Disable
The Brown-out Detector (BOD) can be disabled in certain sleep modes to save power.

Power Reduction Techniques
To minimize power consumption, unnecessary modules should be disabled.

Register Descriptions

SMCR – Sleep Mode Control Register: Controls sleep mode selection and enables sleep mode execution.
MCUCR – MCU Control Register: Manages BOD settings during sleep.
PRR – Power Reduction Register: Allows stopping clocks to individual peripherals to save power.

Power Reduction Features
1. PRTIM0: Shuts down Timer/Counter0 in synchronous mode.

System Control and Reset
Resetting the AVR: During reset, I/O registers are initialized, and the program starts from the reset vector.

Reset Sources: The ATtiny87/167 has four reset sources: Power-on reset, External reset, Watchdog system reset, and Brown-out reset.

Power-on Reset (POR): Triggered when VCC is below the detection level.

External Reset: Generated by a low level on the RESET pin.

Brown-out Detection (BOD): Monitors VCC level, triggering a reset if VCC falls below the trigger level.

Watchdog System Reset: Generates a reset when the watchdog timer expires.

MCU Status Register (MCUSR): Indicates the reset source with flags for Watchdog, Brown-out, External, and Power-on resets.

Internal Voltage Reference: Used for brown-out detection and as input to the analog comparator or ADC.

Watchdog Timer: Features include a separate oscillator, multiple operating modes, and selectable time-out periods.

Watchdog Timer Control Register (WDTCR): Controls the watchdog timer's behavior.

Watchdog Timer Configuration
The document outlines the configuration of the Watchdog Timer (WDT) in the ATtiny87/167 microcontroller.

Interrupts
The document details the interrupt handling mechanisms in the ATtiny87/167.

External Interrupts
External interrupts are managed through several registers.

Pin Change Interrupts
Pin change interrupts are enabled through PCMSK1 and PCMSK0 registers.

Pin Change Enable Mask (PCINT7..0)
Each bit in PCINT7..0 determines if a pin change interrupt is enabled for the corresponding I/O pin.

I/O Ports Overview
AVR ports offer true read-modify-write functionality.

Configuring I/O Ports
Each port pin has three register bits: DDxn, PORTxn, and PINxn.

Break-before-make Switching
When switching a pin from input to output, a tri-state period of one system clock cycle is introduced.

Reading Pin Values
The PINxn register allows reading the pin value.

Digital Input Enable and Sleep Modes
In sleep modes, digital input signals can be clamped to ground to reduce power consumption.

Alternate Port Functions
Port pins may have alternate functions.

Port Control and Override Functions

PVOE (Port Value Override Enable): Controls port value via PVOV signal when set.
PVOV (Port Value Override Value): Sets port value when PVOE is enabled.
PTOE (Port Toggle Override Enable): Inverts PORTxn register bit when set.
DIEOE (Digital Input Enable Override Enable): Controls digital input enable via DIEOV signal when set.
DIEOV (Digital Input Enable Override Value): Enables/disables digital input when DIEOE is set.

Port Control Register (PORTCR)

BBMx (Break-Before-Make Mode Enable): Activates break-before-make mode.
PUDx (Port-Wise Pull-up Disable): Disables port-wise pull-ups.

Alternate Functions of Port A

Each pin on Port A has multiple alternate functions.

Alternate Functions of Port B

Similar to Port A, Port B pins have alternate functions.

Overview: The document provides detailed technical specifications and functionalities of the ATA6616C/ATA6617C microcontroller, focusing on the I/O ports, timer/counter operations, and alternate functions of Port B.

Specifications: The document outlines the functionalities of various pins on Port B.

Register Descriptions: Detailed descriptions of the data registers, data direction registers, and input pins registers for Ports A and B are provided.

8-bit Timer/Counter0: The document describes the features of the 8-bit Timer/Counter0.

Timer/Counter Operations: The document details the clock sources for the Timer/Counter.

Output Compare Unit: The output compare unit's operation is explained.

Compare Match Output Logic: The document describes the logic affected by the compare output mode bits.

Compare Output Function
The output compare (OC0A) function overrides the general I/O port function when COM0A1:0 bits are set.

Compare Output Mode and Waveform Generation
The COM0A1:0 bits are used differently across normal, CTC, and PWM modes.

Modes of Operation
The Timer/Counter behavior is defined by the waveform generation mode (WGM01:0) and compare output mode (COM0A1:0) bits.

Normal Mode
In normal mode (WGM01:0 = 0), the counter increments and restarts from zero after reaching its maximum value (0xFF).

Clear Timer on Compare Match (CTC) Mode
In CTC mode (WGM01:0 = 2), the counter is cleared when TCNT0 matches OCR0A.

Fast PWM Mode
Fast PWM mode (WGM01:0 = 3) generates high-frequency PWM waveforms.

Phase Correct PWM Mode
Phase correct PWM mode (WGM01:0 = 1) uses dual-slope operation for high-resolution waveform generation.

Timer/Counter Timing Diagrams
Timing diagrams illustrate the Timer/Counter operation.

Asynchronous Operation of Timer/Counter0
Switching between asynchronous and synchronous clocking requires careful handling.

Overview: This document provides detailed technical specifications and operational procedures for the Timer/Counter0 in the ATA6616C/ATA6617C microcontroller.

Asynchronous Operation: Timer/Counter0 can operate asynchronously.

Reading TCNT0: To read the TCNT0 register correctly after waking up from power-save mode, a specific procedure must be followed.

Prescaler Settings: Timer/Counter0 can be prescaled with various division factors.

Control Registers: The TCCR0A and TCCR0B registers control the Timer/Counter0 operation.

Interrupt Handling: Timer/Counter0 supports output compare match and overflow interrupts.

General Timer/Counter Control: The GTCCR register includes the PSR0 bit for prescaler reset.

Timer/Counter1 Prescaler Overview
The Timer/Counter can be clocked directly by the system clock or through a prescaler.

Internal and External Clock Sources
The Timer/Counter can use an internal clock or an external clock source.

Timer/Counter1 Prescalers Register Description
The General Timer/Counter Control Register (GTCCR) includes the Timer/Counter Synchronization Mode (TSM) bit.

16-bit Timer/Counter1 Features
The 16-bit Timer/Counter1 supports accurate timing, wave generation, and signal measurement.

Registers and Access
The Timer/Counter1 uses 16-bit registers (TCNT1, OCR1A/B, ICR1).

Clock Sources and Counter Unit
The Timer/Counter can be clocked by internal or external sources.

Timer/Counter Overview
The document provides a detailed explanation of the Timer/Counter functionalities in a microcontroller.

Clock Source and Counting Modes
The counter's behavior is determined by the clock source and mode of operation.

Waveform Generation and Overflow
The waveform generation mode bits (WGM13:0) in control registers TCCR1A and TCCR1B dictate the counting sequence and waveform generation.

Input Capture Unit
The input capture unit timestamps external events via the ICP1 pin or an analog comparator.

Noise Canceler
The noise canceler enhances noise immunity by filtering input signals over four samples.

Output Compare Units
The 16-bit comparator matches TCNT1 with the output compare register (OCR1A/B).

Force Output Compare and Compare Match Blocking
In non-PWM modes, the match output can be forced without affecting the OCF1A/B flag.

Compare Match Output Unit
The COM1A/B1:0 bits define the output compare state.

Overview: This document provides detailed technical specifications and operational modes for a waveform generator.

Specifications: The document outlines the control of waveform generation through the combination of waveform generation mode (WGM13:0) and compare output mode (COM1A/B1:0) bits.

Normal Mode: In this mode, the counter increments continuously and resets upon reaching its maximum value (0xFFFF).

CTC Mode: The CTC mode allows the counter to reset when it matches a specified value in the OCR1A or ICR1 register.

Fast PWM Mode: This mode offers high-frequency PWM waveform generation with single-slope operation.

Phase Correct PWM Mode: Utilizing dual-slope operation, this mode is ideal for motor control applications.

Recommendations: For applications requiring dynamic changes to the TOP value, the phase and frequency correct mode is recommended.

Timer/Counter1 Control and Operation

FOC1A/FOC1B Bits: These bits are active in non-PWM modes.
TCCR1D Register: Controls output compare pin enable for channels A and B.
TCNT1H and TCNT1L Registers: Provide direct access to the 16-bit counter.
OCR1AH/AL and OCR1BH/BL Registers: Contain 16-bit values for output compare.
ICR1H and ICR1L Registers: Capture counter values on events.
TIMSK1 Register: Enables various interrupts.
TIFR1 Register: Contains flags for input capture, output compare, and overflow events.

SPI - Serial Peripheral Interface

Features: Supports full-duplex, three-wire synchronous data transfer.
Master-Slave Interconnection: Involves shift registers and a master clock generator.
Master Mode: The SPI clock generator starts with data register writes.
Slave Mode: The SPI remains passive until the SS pin is low.
Code Examples: Provided for initializing and using SPI in both master and slave modes.

SPI Operation and Configuration

Master and Slave Configuration:
When the SPI is configured as a master, the SS pin must be held high.

SPI Control Register (SPCR):
- SPIE: Enables SPI interrupt execution.
- SPE: Enables SPI operations.
- DORD: Determines data order.
- MSTR: Selects master mode.
- CPOL: Sets clock polarity.
- CPHA: Determines if data is sampled on the leading or trailing edge of SCK.
- SPR1, SPR0: Control the SCK rate in master mode.

SPI Status Register (SPSR):
- SPIF: Set when a serial transfer is complete.
- WCOL: Set if SPDR is written during a data transfer.
- SPI2X: Doubles SPI speed in master mode.

SPI Data Register (SPDR):
Used for data transfer between the register file and the SPI shift register.

Data Modes:
Four combinations of SCK phase and polarity are determined by CPHA and CPOL.

Universal Serial Interface (USI):
Features: Supports two-wire and three-wire synchronous data transfer.

Overview: The USI provides hardware resources for serial communication.

Three-wire Mode: Compliant with SPI mode 0 and 1.

Two-wire Mode: Compliant with the Inter IC (TWI) bus protocol.

Overview: The document provides a detailed technical explanation of the Universal Serial Interface (USI) operation in two-wire mode.

Specifications: The master device is responsible for generating the serial clock.

Procedures: The document outlines the steps involved in a typical bus transfer.

Registers and Flags: The document details the USI Data Register (USIDR), Buffer Register (USIBR), Status Register (USISR), and Control Register (USICR).

Alternative USI Usage: The USI can be configured for alternative tasks.

Key Diagrams: The document includes timing diagrams and logic diagrams.

Recommendations: The document suggests implementing a protocol similar to the TWI-bus.

USI Clock and Pin Position:
The document describes the configuration of the Universal Serial Interface (USI) clock and pin position settings.

LIN/UART Controller:
The document details the Local Interconnect Network (LIN) and Universal Asynchronous Receiver-Transmitter (UART) functionalities.

LIN Protocol:
The LIN protocol involves a master node and multiple slave nodes.

LIN/UART Controller Functions:
The controller is divided into functions for transmitting and receiving LIN headers and responses.

UART Commands
UART commands are enabled by setting the LCMD[2] bit in the LINENR register.

Rx Service
When enabled, the LRXOK flag indicates an incoming character.

Tx Service
In Tx mode, writing to the LINDAT register sends a character.

LIN/UART Description
The LIN/UART controller resets with the AVR core or via a software reset.

Busy Signal
The LBUSY flag indicates active communication.

Bit Timing
The baud rate is determined by the system I/O clock frequency and register values.

Data Length
Data length settings differ between LIN 2.1 and LIN 1.3.

xxOK and xxERR Flags
The LINSIR register contains flags indicating successful operations and errors.

Frame Time Out
A frame time-out error occurs if the frame exceeds the maximum length.

Frame Abortion and Error Handling
In the event of a frame abortion, the master node is responsible for aborting the ongoing communication.

Checksum Calculation
The checksum is the last field of a frame.

Interrupts and Message Filtering
The LINSIR register's communication flags drive two interrupts.

Data Management
The LIN data buffer operates as a FIFO.

LIN/UART Register Description
The document provides a detailed description of various LIN/UART registers.

Current Source Features
The Atmel ATtiny87/167 features a 100µA constant current source.

LIN Current Source Configuration
During the configuration of a LIN node in a cluster, assigning a unique physical address to each node is necessary.

Resistor Values for Address Systems
Tables provide resistor values for 8-address and 16-address systems.

Current Source Applications
The current source can be used with external transducers.

Control Register
The AMISCR register controls the current source.

ADC Features and Operation
The ATtiny87/167 features a 10-bit ADC with various input channels.

ADC Conversion Process
The ADC converts analog input to a digital value.

ADC Timing and Prescaling
The ADC requires a clock frequency between 50kHz and 200kHz for maximum resolution.

Changing Channel or Reference Selection: The MUX[4:0] and REFS[1:0] bits in the ADMUX register are buffered.

ADC Input Channels: In single conversion mode, select the channel before starting conversion.

ADC Voltage Reference: VREF can be AVCC, internal 1.1V/2.56V, or external AREF.

ADC Noise Canceler: Enables conversion during sleep mode to reduce noise.

Analog Input Circuitry: Optimized for signals with output impedance of 10kΩ or less.

Analog Noise Canceling Techniques: Shorten analog signal paths.

ADC Accuracy Definitions: Describes offset, gain error, integral non-linearity (INL), differential non-linearity (DNL), quantization error, and absolute accuracy.

ADC Conversion Result: Results vary based on conversion type.

Temperature Measurement: Uses an on-chip sensor with a linear relationship to temperature.

Internal Voltage Reference Output: Output on XREF pin with specific current load requirements.

Register Description: ADMUX register controls voltage reference selection.

Voltage Reference Output: The document outlines configurations for voltage reference outputs.

ADC Control and Status Registers: The document describes the ADC Control and Status Register A (ADCSRA).

ADC Data Registers: The ADC Data Registers (ADCL and ADCH) store the results of ADC conversions.

ADC Prescaler Selections: The document provides a table for ADC prescaler selections.

Analog Comparator: The document describes the functionality of the analog comparator.

Digital Input Disable Registers: The DIDR0 and DIDR1 registers are discussed.

Miscellaneous Control Register: The AMISCR register is mentioned.

Analog Comparator Inputs

Positive Input: The ADC multiplexer can replace the positive input to the analog comparator.
Negative Input: An internal voltage reference can replace the negative input.

DebugWIRE On-chip Debug System

Features: Includes program flow control, real-time operation, symbolic debugging, and high-speed operation.
Physical Interface: Activated by programming the DWEN Fuse.
Software Break Points: Uses the AVR BREAK instruction.
Limitations: External reset sources are unsupported when debugWIRE is enabled.

Flash Programming

Self-programming: The device can self-program using interfaces like LIN or USART.
Page Erase and Write: Executed by setting specific bits in the SPMCSR register.
Addressing: Uses the Z-pointer to address SPM commands.
SPMCSR Register: Controls boot loader operations.

Fuse and Lock Bits: The document describes the process of reading and programming fuse and lock bits.

Reading Signature Row: To read the signature row, the Z-pointer is loaded with the signature byte address.

Preventing Flash Corruption: Flash corruption can occur during low VCC periods.

Programming Time: The document provides typical programming times for flash accesses.

Assembly Code Example: A simple assembly code example for a boot loader is provided.

Memory Programming: The ATtiny87/167 provides two lock bits for additional features.

Fuse Bits: The microcontroller has three fuse bytes.

Signature and Calibration Bytes: The microcontroller has a three-byte signature code and a calibration byte.

Parallel Programming: The document describes the process for entering programming mode.

Chip Erase Procedure:

Enable command loading by setting XA1, XA0 to "1,0".
Set BS1 to "0" and DATA to "1000 0000 b" for chip erase command.
Load the command with a positive pulse on XTAL1 and start chip erase with a negative pulse on WR.
Wait for RDY/BSY to go high before loading a new command.

Flash Programming:

Flash is organized in pages; program data is latched into a page buffer.
Load "Write Flash" command by setting XA1, XA0 to "1,0" and DATA to "0001 0000 b".
Load address and data bytes sequentially, latch data, and program the page with a negative pulse on WR.
Repeat the process until the entire Flash is programmed.

EEPROM Programming:

EEPROM is also organized in pages; follow a similar procedure as Flash programming.
Load command, address, and data bytes, latch data, and program EEPROM page.

Reading Procedures:

Flash and EEPROM reading involves loading specific commands and addresses, then reading data at DATA.

Fuse and Lock Bits Programming:

Load specific commands and data bytes to program fuse and lock bits.
Lock bits can only be cleared by executing chip erase.

Serial Downloading:

Flash and EEPROM can be programmed using the serial SPI bus.
Ensure correct synchronization and follow the power-up sequence for programming.

Serial Programming Algorithm:

Power-up sequence involves applying power while holding RESET and SCK low.
Enable serial programming by sending the programming enable instruction.
Program Flash and EEPROM by loading pages and verifying with read instructions.

EEPROM and Program Memory Access Instructions
Instructions for reading and writing EEPROM and program memory are provided.

Notes and Recommendations
1. Not all instructions apply to all parts.
2. Addressing uses specific bit patterns.
3. Programmed bits are '0', unprogrammed are '1'.
4. Unused fuses and lock bits should remain unprogrammed for compatibility.
5. Refer to specific sections for detailed information on fuses, lock bits, and page sizes.
6. Program memory instructions use word addresses.
7. Application notes are available on the Atmel website.

Serial Programming Characteristics
Details on serial programming waveforms and characteristics are provided.

Electrical Characteristics
DC characteristics are outlined for various conditions.

Clock and Reset Characteristics
Information on internal RC oscillator accuracy, external clock drive waveforms, and reset characteristics is provided.

Internal Voltage and ADC Characteristics
Characteristics of internal voltage references and ADC performance are detailed.

Parallel Programming Characteristics
Timing requirements for parallel programming operations are specified.

SPI Timing Characteristics
The document outlines the SPI timing characteristics for both master and slave modes.

Decoupling Capacitors
The section discusses the importance of decoupling capacitors in microcontroller design.

Typical Characteristics
This section provides insights into the typical behavior of the device.

Register Summary
A comprehensive summary of register addresses and their functions is provided.

Register Summary:
This section provides a detailed list of registers for the ATA6616C/ATA6617C microcontrollers.

Instruction Set Summary:
The document outlines various arithmetic, logic, branch, and bit manipulation instructions available for the microcontroller.

Key Notes:
- Reserved bits should be written to zero if accessed.
- I/O addresses 0x00 - 0x3F must be used with IN and OUT commands.
- Extended I/O space requires specific instructions like ST/STS/STD and LD/LDS/LDD.
- Status flags can be cleared by writing a logical one to them.

Instruction Set Summary:
The document provides a detailed summary of the instruction set for the ATA6616C/ATA6617C microcontrollers.

Application Examples:
The document includes several application examples for LIN (Local Interconnect Network) configurations.

Package and Ordering Information:
The document outlines the package specifications for the ATA6616C/ATA6617C.

Revision History:
The document includes a revision history, detailing updates and changes made in various sections over time.

Flash Programming: This section details the procedures and specifications for programming the flash memory of the device.

Memory Programming: This part outlines the methods for programming the device's memory.

Electrical Characteristics: This section provides a comprehensive overview of the electrical specifications of the device.

Decoupling Capacitors: The document discusses the role and specifications of decoupling capacitors.

Typical Characteristics: This section presents typical performance metrics and characteristics of the device.

Register Summary: A detailed summary of the device's registers is provided.

Instruction Set Summary: The document includes a summary of the instruction set used by the device.

Application: This section explores potential applications of the device.

Ordering Information: Details on how to order the device are provided.

Package Information: Information about the physical packaging of the device is included.

Revision History: A record of document revisions is provided.

Disclaimer: The document includes a disclaimer regarding the use of Atmel products.

Catalog excerpts

ATA6616C/ATA6617C 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog DATASHEET General Features ● Single-package high performance, low power AVR® 8-bit microcontroller with LIN transceiver, 5V regulator (85mA current capability) and watchdog ● Very low current consumption in sleep mode ● 8Kbytes/16Kbytes flash memory for application program (Atmel® ATA6616C/ATA6617C) ● Supply voltage up to 40V ● Operating voltage: 5V to 27V ● Temperature range: Tcase –40°C to +125°C ● QFN38, 5mm 7mm package Description Atmel ATA6616C/ATA6617C is a System-in-Package (SiP) product, which is particularly suited for complete LIN-bus node applications. It consists of two ICs in one package supporting highly integrated solutions for in-vehicle LIN networks. The first chip is the LINsystem-basis-chip (LIN-SBC) ATA6624, which has an integrated LIN transceiver, a 5V regulator (85mA) and a window watchdog. The second chip is an automotive microcontroller from Atmel’s series of AVR 8-bit microcontroller with advanced RISC architecture, the Atmel ATtiny87 with 8-Kbytes and the Atmel ATtiny167 with 16-Kbytes flash memory. All pins of the LIN system basis chip as well as all pins of the AVR microcontroller are bonded out to provide customers the same flexibility for their applications as they have when using discrete parts. In Section 1. “Atmel ATA6616C/ATA6617C LIN System in Package Solution (SIP)” on page 3 you will find the pin configuration for the complete SiP. In Section 3. “LIN System-basischip Block” on page 7 the LIN SBC is described, and in Section 4. “Atmel ATtiny87/ATtiny167 Microcontroller Block for Atmel ATA6616C/ATA6617C” on page 26 the AVR is described in detail.

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Application Diagram LIN-bus Atmel ATA6616C/ATA6617C MCU Atmel ATtiny 87/167

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Atmel ATA6616C/ATA6617C LIN System in Package Solution (SIP) NRES WD_OSC Receive data output Battery-related output for controlling an external voltage regulator Transmit data input; active low output (strong pull down) after a local wake-up request (1) Output undervoltage and watchdog reset (open drain) External resistor for adjustable watchdog timing For factory testing only (tie to ground) Ignition detection (edge sensitive) 5V regulator sense input pin For debug mode: Low watchdog is on; high watchdog is off 5V regulator output/driver pin Battery supply Enables the device into normal mode...

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Table 1-1. Pin Description (Continued) Note:1 This identifies the pins of the LIN SBC Atmel® ATA6624

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Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters ESD according to IBEE LIN EMC Test Spec. 1.0 following IEC 61000-4-2 - Pin VS, LIN, KL_15 (47k/100nF) to GND - Pin WAKE (33 k serial resistor) to GND ESD HBM following STM5.1...

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Maximum Ratings of the LIN-SBC (Continued) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Logic pins (RXD, TXD, EN, NRES, NTRIG, WD_OSC, MODE, TM) Output current NRES PVCC DC voltage VCC DC voltage Table 2-3. Maximum Ratings of the Microcontroller...

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Master and slave operation possible Supply voltage up to 40V Operating voltage VS = 5V to 27V Typically 10µA supply current during sleep mode Typically 57µA supply current in silent mode Linear Low-drop voltage regulator, 85mA current capability: ● Normal, fail-safe, and silent mode In sleep mode VCC is switched off VCC undervoltage detection (4ms reset time) and watchdog reset logical combined at open drain output NRES Negative trigger input for watchdog Boosting the voltage regulator possible with an external NPN transistor LIN physical layer according to LIN 2.0, 2.1 specification and SAEJ2602-2...

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Figure 3-1. Block Diagram VS Normal and Fail-safe Mode Normal Mode Edge Detection Slew Rate Control Control Unit Short Circuit and Overtemperature Protection Debounce Time Normal/Silent/ Fail-safe Mode 5V Undervoltage Reset Mode Select Internal Testing Unit Adjustable Watchdog Oscillator

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Functional Description Physical Layer Compatibility Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer nodes, which are according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), without any restrictions. Supply Pin (VS) The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable data transmission if VS falls below VSth < 4V in order to avoid false bus messages. After switching on VS, the IC starts...

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Output Pin (RXD) The Output pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typically 5k to VCC. The AC characteristics can be defined with an external load capacitor of 20pF. The output is short-circuit protected. RXD is switched off in Unpowered Mode (i.e., VS = 0V). 3.3.10 Enable Input Pin (EN) The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in normal mode with transmission...

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3.3.18 NTRIG Input Pin The NTRIG Input pin is the trigger input for the window watchdog. A pull-up resistor is implemented. A negative edge triggers the watchdog. The trigger signal (low) must exceed a minimum time ttrigmin to generate a watchdog trigger. 3.3.19 Wake-up Events from Sleep or Silent Mode ● ● ● ● Modes of Operation Figure 3-2. Modes of Operation a: VS > 5V Unpowered Mode VBatt = 0V b: VS < 4V c: Bus wake-up event d: Wake up from WAKE or KL_15 pin Fail-safe Mode VCC: 5V With undervoltage monitoring Communication: OFF Watchdog: ON Silent Mode VCC: 5V With undervoltage monitoring Communication:...

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