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AT90PWM216/316

AT90PWM216/316
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AT90PWM216/316

Product catalog summary
Overview: The AT90PWM216/316 is a high-performance, low-power 8-bit microcontroller based on the AVR enhanced RISC architecture, capable of executing powerful instructions in a single clock cycle, achieving up to 1 MIPS per MHz. It is designed for applications requiring efficient power consumption and processing speed.
Specifications:
  • 16K Bytes of In-System Programmable Flash with 10,000 write/erase cycles endurance.
  • 512 Bytes of EEPROM with 100,000 write/erase cycles endurance.
  • 1024 Bytes of internal SRAM.
  • Operating voltage range: 2.7V - 5.5V.
  • Operating temperature range: -40°C to +105°C.
Architectural Features:
  • Advanced RISC architecture with 129 powerful instructions.
  • 32 x 8 general-purpose working registers.
  • On-chip 2-cycle multiplier.
  • On-chip debug interface (debugWIRE).
Peripheral Features:
  • Two or three 12-bit high-speed Power Stage Controllers (PSC) with 4-bit resolution enhancement.
  • One 8-bit and one 16-bit general-purpose Timer/Counter.
  • Programmable Serial USART and Master/Slave SPI Serial Interface.
  • 10-bit ADC with up to 11 single-ended channels and 2 differential channel pairs.
  • 10-bit DAC and multiple analog comparators.
Special Microcontroller Features:
  • Low power idle, noise reduction, and power-down modes.
  • Power-on reset and programmable brown-out detection.
  • Internal calibrated RC oscillator (8 MHz) and on-chip PLL for fast PWM and CPU operation.
Pin Configurations: Detailed pin configurations for SOIC 24-pin, SOIC 32-pin, and QFN32 packages are provided, including descriptions of each pin's function and alternate functions.
Development Support: Supported by a full suite of development tools, including C compilers, macro assemblers, program debuggers/simulators, in-circuit emulators, and evaluation kits.
ALU Operations: The ALU performs arithmetic and logic operations between registers or between a constant and a register within a single clock cycle, updating the Status Register to reflect the result.
Register File: Includes 32 general-purpose registers, with six registers serving as 16-bit indirect address pointers (X, Y, Z registers) for efficient data space addressing.
Program Memory: Divided into Boot and Application sections, each with dedicated Lock bits for protection. The SPM instruction for writing into Application Flash must reside in the Boot section.
Stack and Stack Pointer: The Stack is used for storing temporary data and return addresses, growing from higher to lower memory locations. The Stack Pointer, implemented as two 8-bit registers, must be initialized by the user program.
Instruction Execution Timing: The AVR CPU uses a pipelined architecture to achieve up to 1 MIPS per MHz. Instructions are fetched and executed in parallel, with most instructions completing in a single cycle.
Interrupt Handling: Supports multiple interrupt sources, each with a separate vector in program memory. Interrupts are prioritized by vector address, with the lowest address having the highest priority.
Status Register: Contains flags such as Global Interrupt Enable, Half Carry, Sign, Overflow, Negative, Zero, and Carry, which provide information about the result of ALU operations.
Memory Architecture: Features three main memory spaces: Data Memory, Program Memory, and EEPROM Memory. Program Memory consists of 16K bytes of In-System Reprogrammable Flash, organized as 8K x 16, with a minimum endurance of 10,000 write/erase cycles.
EEPROM Access and Programming: The EEPROM can be accessed through specific registers, and a detailed procedure must be followed to prevent unintentional writes.
Preventing EEPROM Corruption: To prevent EEPROM data corruption during low voltage conditions, it is recommended to keep the AVR RESET active.
I/O Memory: Accessible through specific instructions, allowing data transfer between general-purpose registers and the I/O space.
Clock Systems: Describes various clock systems, including the CPU clock (clkCPU), I/O clock (clkI/O), Flash clock (clkFLASH), PLL clock (clkPLL), and ADC clock (clkADC).
Oscillator and Calibration: Features a low power Crystal Oscillator and a Calibrated Internal RC Oscillator, which can be fine-tuned using the OSCCAL register.
Power Management and Sleep Modes: Five sleep modes available: Idle, ADC Noise Reduction, Power-down, Power-save, Standby.
Power Reduction Register (PRR): Allows stopping the clock to individual peripherals to reduce power consumption.
Minimizing Power Consumption: Recommended to use sleep modes extensively and disable unnecessary functions.
System Control and Reset: The AVR system has several reset sources, including Power-on Reset, External Reset, Watchdog Reset, and Brown-out Reset.
Watchdog Timer: Features an Enhanced Watchdog Timer (WDT) with three operating modes: Interrupt, System Reset, and Interrupt and System Reset.
Watchdog Timer Overview: Provides detailed instructions on handling the Watchdog Timer (WDT) in AT90PWM216/316 microcontrollers.
Analog Comparator: Features three fast analog comparators with configurable inputs and interrupt capabilities.
Analog Comparator Control Registers: Details the control registers for three analog comparators (AC0, AC1, AC2) in the AT90PWM216/316 microcontroller.
ADC Module Overview: The ADC module includes a prescaler to generate an acceptable ADC clock frequency from any CPU frequency above 100 kHz.
ADC Operation and Configuration: Converts analog input to a digital value using successive approximation.
ADC Input Channels and Voltage Reference: Channel selection should be done before starting conversions.
ADC Characteristics: Include resolution, accuracy, and conversion times.
Amplifier Specifications: Features two differential amplified channels with programmable gain stages (5, 10, 20, 40).
Amplifier Control Registers: Control the configuration of amplifiers, including enabling/disabling, input shunt, and gain settings.
Digital to Analog Converter (DAC) Features and Operation: Features a 10-bit resolution and can be connected to analog comparators or output via a dedicated driver.
debugWIRE On-chip Debug System: Provides program flow control and supports real-time operation with symbolic debugging.
Boot Loader Support: Supports Read-While-Write Self-Programming, allowing the MCU to update application software via a Flash-resident Boot Loader program.
Flash Memory Organization: Divided into two main sections: the Application section and the Boot Loader section.
Read-While-Write and No Read-While-Write Sections: The Flash is further divided into Read-While-Write (RWW) and No Read-While-Write (NRWW) sections.
Boot Loader Lock Bits: The Boot Loader has two sets of Boot Lock bits for flexible protection levels.
Programming the Flash and EEPROM: Provides detailed instructions for programming the Flash and EEPROM memory of the AT90PWM216/316 microcontroller.
Programming the EEPROM: Organized in pages, allowing simultaneous programming of one page.
Reading the Flash and EEPROM: To read the Flash memory, specific commands and addresses are loaded, and the data is read by setting control signals.
Programming Fuse and Lock Bits: Outlines algorithms for programming the Fuse Low, High, and Extended bits, as well as the Lock bits.
Serial Downloading: The Flash and EEPROM can be programmed using the serial SPI bus.
Timing and Characteristics: Provides timing requirements and characteristics for parallel and serial programming.
Branch Instructions: Outlines various branch instructions for the AT90PWM216/316 microcontroller.
Bit and Bit-Test Instructions: Instructions like SBI (Set Bit in I/O Register) and CBI (Clear Bit in I/O Register) are detailed.
Data Transfer Instructions: Describes instructions for moving data between registers and memory.
MCU Control Instructions: Instructions like NOP (No Operation) and SLEEP (Sleep mode) are included.
Ordering and Package Information: Details on ordering codes, package types, and operational ranges for different configurations of the AT90PWM216/316 are provided.
Errata: Notes an issue with DAC driver linearity above 3.6V and suggests workarounds.
Datasheet Revision History: Updates and changes across different revisions of the datasheet are listed.
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Catalog excerpts

AT90PWM216/316-1

> High Performance, Low Power AVR ծ 8-bit Microcontroller > Advanced RISC ArchitectureՖ129 Powerful Instructions - Most Single Clock Cycle Execution32 x 8 General Purpose Working Registers֖Fully Static Operation Up to 1 MIPS throughput per MHz֖On-chip 2-cycle Multiplier > Data and Non-Volatile Program MemoryՖ16K Bytes Flash of In-System Programmable Program Memory Endurance: 10,000 Write/Erase CyclesՖOptional Boot Code Section with Independent Lock Bits > In-System Programming by On-chip Boot Program Օ > True Read-While-Write Operation512 Bytes of In-System Programmable EEPROM ֕ > Endurance: 100,000 Write/Erase Cycles1024 Bytes Internal SRAM ֖Programming Lock for Flash Program and EEPROM Data Security > On Chip Debug Interface (debugWIRE) Օ > Peripheral FeaturesTwo or three 12-bit High Speed PSC (Power Stage Controllers) with 4-bit Resolution Enhancement֕Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time Variable PWM duty Cycle and Frequency ՕSynchronous Update of all PWM RegistersAuto Stop Function for Event Driven PFC ImplementationՕLess than 25 Hz Step Width at 150 kHz Output Frequency PSC2 with four Output Pins and Output MatrixՖOne 8-bit General purpose Timer/Counter with Separate Prescaler and Capture ModeOne 16-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode and Capture Mode֖Programmable Serial USARTStandard UART mode Օ16/17 bit Biphase Mode for DALI CommunicationsMaster/Slave SPI Serial Interface ֖10-bit ADCUp To 11 Single Ended Channels and 2 Fully Differential ADC Channel PairsՕProgrammable Gain (5x, 10x, 20x, 40x on Differential Channels) Internal Reference VoltageՖ10-bit DACTwo or three Analog Comparator with Resistor-Array to Adjust Comparison Voltage֖4 External Interrupts Programmable Watchdog Timer with Separate On-Chip Oscillator ֕ > Special Microcontroller FeaturesLow Power Idle, Noise Reduction, and Power Down Modes֖Power On Reset and Programmable Brown Out Detection Flag Array in Bit-programmable I/O Space (4 bytes) 7710C֖AVR01/08 size="-2">

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AT90PWM216/316-2

In-System Programmable via SPI Port֖Internal Calibrated RC Oscillator ( 8 MHz)On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz) > Extended Operating Temperature: Ֆ-40C to +105а ProductPackage12 bit PWM with deadtimeADC InputADC DiffAnalog ComparApplication AT90PWM216SO242 x 2812One fluorescent ballastAT90PWM316SO32, QFN32 3 x 21123HID ballast, fluorescent ballast, Motor control > ProductRevision AT90PWM216AT90PWM316First revision of parts >

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AT90PWM216/316-3

Figure 3-1. SOIC 24-pin Package Figure 3-2. SOIC 32-pin Package 3 > 7710CAVR֖01/08 size="-1">

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AT90PWM216/316-5

S024 Pin NumberSO32 Pin NumberQFN32 Pin NumberMnemonicTypeName, Function & Alternate Function 684VCCpower Power Supply: 172319AVCCPower Analog Power Supply: This is the power supply voltage for analog partFor a normal use this pin must be connected.192521AREFPower Analog Reference : reference for analog converter . This is the reference voltage of the A/D converter. As output, can be used by external analog8128PBOI/OMISO (SPI Master In Slave Out)PSCOUT20 output9139PB1I/OMOSI (SPI Master Out Slave In)PSCOUT21 output162016PB2I/OADC5 (Analog Input Channel5 )INT1202723PB3I/OAMP0- (Analog Differential...

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AT90PWM216/316-6

Table 3-1. Pin out description (Continued) > S024 Pin NumberSO32 Pin NumberQFN32 Pin NumberMnemonicTypeName, Function & Alternate Function 1129PD0I/OPSCOUT00 outputXCK (UART Transfer Clock) SS_A (Alternate SPI Slave Select)3432PD1I/OPSCIN0 (PSC 0 Digital Input )CLKO (System Clock Output)451PD2I/OPSCIN2 (PSC 2 Digital Input) OC1A (Timer 1 Output Compare A) MISO_A (Programming & alternate SPI Master In Slave Out)562PD3I/OTXD (Dali/UART Tx data)OC0A (Timer 0 Output Compare A) SS (SPI Slave Select) MOSI_A (Programming & alternate Master Out SPI Slave In)121612PD4I/OADC1 (Analog Input Channel 1)RXD...

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AT90PWM216/316-8

The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports and interruptsystem to continue functioning. The Power-down mode saves the register contents but freezesthe Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. TheADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switch-ing noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is runningwhile the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured...

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AT90PWM216/316-9

4.2.5Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort D output buffers have symmetrical drive characteristics with both high sink and sourcecapability. As inputs, Port D pins that are externally pulled low will source current if the pull-upresistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.Port D also serves the functions of various special features of the AT90PWM216/316 as listedon page 73. 4.2.6Port E (PE2..0) RESET/ XTAL1/XTAL2 Port E is...

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AT90PWM216/316-11

The fast-access Register File contains 32 x 8-bit general purpose working registers with a singleclock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-ical ALU operation, two operands are output from the Register File, the operation is executed,and the result is stored back in the Register File in one clock cycle.Six of the 32 registers can be used as three 16-bit indirect address register pointers for DataSpace addressing ֖ enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up...

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AT90PWM216/316-15

Figure 5-4. The Parallel Instruction Fetches and Instruction Executions Figure 5-5 shows the internal timing concept for the Register File. In a single clock cycle an ALUoperation using two register operands is executed, and the result is stored back to the destina- tion register. > T1T2T3T4 clk1st Instruction Fetch1st Instruction Execute2nd Instruction Fetch2nd Instruction Execute3rd Instruction Fetch3rd Instruction Execute4th Instruction Fetch CPU Figure 5-5. Single Cycle ALU Operation > T1T2T3T4 clk CPU Total Execution TimeRegister Operands FetchALU Operation ExecuteResult Write Back The AVR...

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