High Performance RF-CMOS 2.4 GHz Radio Transceiver Targeted for IEEE 802.15.4 and ZigBee Applications Օ Industry Leading Link Budget (104 dB): - Programmable Output Power from -17 dBm up to 3 dBm - Receiver Sensitivity -101 dBm Ultra-Low Power Consumption: - SLEEP: 20 nA - RX: 15.5 mA - TX: 16.5 mA (at max Transmit Power of 3 dBm) > ٕ Ultra-Low Supply Voltage (1.8V to 3.6V) with Internal Regulator Optimized for Low BoM Cost and Ease of Production: - Few External Components Necessary (Crystal, Capacitors and Antenna) Օ Excellent ESD Robustness Easy to Use Interface: - Registers and Frame Buffer Accessible through Fast SPI - Only Two Microcontroller GPIO Lines Necessary - One Interrupt Pin from Radio Transceiver - Clock Output with Prescaler from Radio Transceiver Օ Radio Transceiver Features: - 128-byte SRAM for Data Buffering - Programmable Clock Output to Clock the Host Microcontroller or as Timer Reference > - Integrated TX/RX Switch - Fully Integrated PLL with on-chip Loop Filter - Fast PLL Settling Time - Battery Monitor - Fast Power-Up Time < 1 ms Special IEEE 802.15.4-2003 Hardware Support: - FCS Computation - Clear Channel Assessment - Energy Detection / RSSI Computation - Automatic CSMA-CA - Automatic Frame Retransmission - Automatic Frame Acknowledgement - Automatic Address Filtering Օ Industrial Temperature Range: - -40 C to 85а C I/O and Packages: - 32-pin Low-Profile QFN - RoHS/Fully Green Օ Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210 > Compliant to IEEE 802.15.4-2003 > 5131D-ZIGB-12/03/07 1 > 5131D-ZIGB-12/03/07 size="-2">

FTN DCLK AVREG TX powercontrol XOSC DVREG IRQ BATMON PA Frequency Synthesis > SEL RFPRFN TX Data TX BBP Control Logic/Configuration Registers SPISlaveInterface SCLKMISOMOSI > IQ LNA PPF SSBF Limiter ADC RX BBP Fame Buffer CLKM RSSI SLP_TR AGC >

RST Digital input Chip reset; active low 9 DVSS Ground Digital ground 10 DVSS Ground Digital ground 11 SLP_TR Digital input Controls sleep, transmit start and receive states; active high 12 DVSS Ground Digital ground 13 DVDD Supply Regulated 1.8V supply voltage; digital domain 14 DVDD Supply Regulated 1.8V supply voltage; digital domain 15 DEVDD Supply External supply voltage; digital domain 16 DVSS Ground Digital ground 17 CLKM Digital output Master clock signal output 18 DVSS Ground Digital ground 19 SCLK Digital input SPI clock 20 MISO Digital output SPI data output (master input slave output)...

AVDD, DVDD AVDD and DVDD are outputs of the internal 1.8V voltage regulators. The voltage regulators are controlled independently by the radio transceivers state machine and are activated depending on the current radio transceiver state. The voltage regulators can be configured for external supply. For details refer to section 9.4. AVSS, DVSS AVSS and DVSS are analog and digital ground pins respectively. The analog and digital power domains should be separated on the PCB, for further details see application note AVR2005 "Design Considerations for the AT86RF230". > RFP, RFN A differential RF port...

In receive mode, the RF input provides a low-impedance path to ground when transistor M0 (see Figure 4-1) pulls the inductor center tap to ground. A DC voltage drop of 20 mV across the on-chip inductor can be measured at the RF pins. In transmit mode, a control loop provides a common-mode voltage of 0.9V. Transistor M0 is off, allowing the PA to set the common-mode voltage. The common-mode capacitance at each pin to ground shall be < 30 pF to ensure the stability of this common-mode feedback loop. The pin XTAL1 is the input of the reference oscillator amplifier (XOSC), XTAL2 is the output. A...

4.3.2 Pull-up and Pull-down Configuration of Digital Input Pins Pulling resistors are internally connected to all digital input pins in radio transceiver state P_ON (see section 7.1.2). Table 4-4 summarizes the pull-up and pull-down configuration. Table 4-4 Pull-Up/Pull-Down Configuration of Digital Input Pins in P_ON State > Pin H RST H SEL H SCLK L MOSI L pull-up, L pull-down SLP_TR L In all other radio transceiver states, no pull-up or pull-down resistors are connected to any of the digital input pins. 4.3.3 Register Description Register 0x03 (TRX_CTRL_0) The TRX_CTRL_0 register controls the...

Table 4-6. CLKM Driver Strength > Register Bit Value Description PAD_IO_CLKM 3 8 mA 0 2 mA 1 4 mA 2 6 mA Bit 3 Ֆ CLKM_SHA_SEL Refer to section 9.6.5. Bit [2:0] Ֆ CLKM_CTRL Refer to section 9.6.5. > An application circuit of the AT86RF230 radio transceiver with a single-ended RF connector is shown in Figure 5-1. The balun B1 transforms the 100 single-ended RF port. The capacitors C1 and C2 provide AC coupling of the RF signals to the RF pins. Figure 5-1. Application Circuit Schematic differential RF port (RFP/RFN) to a 50 > SEL RST 8 >

B1 SMD balun 2.4 GHz Wuerth 748421245 CB1 LDO VREG bypass capacitor 1 յF CB2 Power supply decoupling 1 F CB3 LDO VREG bypass capacitor 1 յF CB4 Power supply decoupling 1 F AVX Murata 0603YD105KAT2A GRM188R61C105KA12D X5R 10% 16V (0603) CX1 Crystal load capacitor 12 pF CX2 Crystal load capacitor 12 pF AVX Murata 06035A120JA GRP1886C1H120JA01 COG 5% 50V (0603) C1 RF coupling capacitor 22 pF C2 RF coupling capacitor 22 pF Epcos Epcos AVX B37930 B37920 06035A220JAT2A C0G 5% 50V (0402 or 0603) C3 CLKM low-pass filter capacitor 2.2 pF AVX Murata 06035A229DA GRP1886C1H2R0DA01 COG > 0.5 pF 50V (0603)...

The SPI is designed to work in synchronous or asynchronous mode. In synchronous mode, the CLKM output of the radio transceiver is used as the master clock of the microcontroller. In this case the maximum SPI clock frequency is 8 MHz. In asynchronous mode, the SPI master clock (SCLK) is generated by the microcontroller itself. The maximum SPI clock rate is limited to 7.5 MHz using this operating mode. If the clock signal from the radio transceiver pin CLKM is not required, it may be disabled. Figure 6-2 and Figure 6-3 illustrate the SPI timing and introduce its parameters. The corresponding timing...