AT17F16A 16 Mbit In-System Programable PROM (3.3V) for Altera.
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AT17F16A FPGA Configuration Flash Memory DATASHEET Features Programmable 16,777, 216 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) 3.3V Output Capability 5.0V Tolerant I/O Pins Program Support using the Atmel ATDH2200E System, ATDH2225 ISP Cable, or Third-party Programmers In-System Programmable (ISP) via 2-wire Bus Simple Interface to SRAM FPGAs Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, Excalibur™, Stratix®, Cyclone™ and APEX™ Devices Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Low-power CMOS FLASH Process Available in 8-pad LAP and 20-lead PLCC Packages Emulation of the Atmel AT24C Serial EEPROMs Low-power Standby Mode Single Device Capable of Holding Four Bitstream Files Allowing Simple System Reconfiguration Fast Serial Download Speeds up to 33MHz Endurance: 10,000 Write Cycles Typical Green (Pb/Halide-free/RoHS Compliant) Packages Description The Atmel® AT17F16A In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory solution for FPGAs. The AT17F16A is packaged in the 8-pad LAP and 20-lead PLCC (Table 1). The AT17F16A uses a simple serial-access procedure to configure one or more FPGA devices. The AT17F16A can be programmed with industry-standard programmers, the Atmel ATDH2200E Programming Kit, or the Atmel ATDH2225 ISP Cable. Table 1.

Three-state DATA output for FPGA Configuration. Open-collector bi-directional pin for configuration programming. Three-state Clock. Functions as an input when the Configurator is in programming mode (i.e. SER_EN is Low) and as an output during FPGA configuration. Enable Page Download Mode Input. When PAGE_EN is high the configuration download address space is partitioned into four equal pages. This gives users the ability to easily store and retrieve multiple configuration bitstreams from a single configuration device. This input works in conjunction with the PAGESEL inputs. PAGE_EN must be...

Paging Decodes

Block Diagram Figure 2-1. Block Diagram Page Select Serial Download Logic Control Logic

Device Description The control signals for the configuration memory device (nCS, RESET/OE and DCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration device without requiring an external intelligent controller. The RESET/OE and nCS pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin. The nCS pin also controls the output of the AT17F16A. If...

Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. The AT17F16A is read/write at 3.3V nominal. Refer to the AT17F(A) Programming Specification available on www.atmel.com for more programming details. AT17F16A is supported by the Atmel ATDH2200 programming system along with many third party programmers. Standby Mode The AT17F16A enters a low-power standby mode whenever SER_EN is High and nCS is asserted...

Electrical Specifications Absolute Maximum Ratings* Operating Temperature . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Voltage on Any Pin with Respect to Ground . . . . . . . . . . . . . . . . .-0.5V to VCC +0.5V Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.0V Maximum Soldering Temp. (10 sec. @ 1/16in.) . . . . . . . . .260C ESD (RZAP = 1.5K, CZAP = 100pF) . . . . . . . . . . . . . . . . . . 2000V *Notice: Stresses beyond those listed under Absolute Maximum Ratings may cause...

DCLK to Data Delay Data Hold from nCS, OE, or DCLK nCS or OE to Data Float Delay DCLK High Time nCS Setup Time to DCLK (to guarantee proper counting) nCS Hold Time from DCLK (to guarantee proper counting) RESET/OE Low Time (guarantees counter is reset) Maximum Input Clock Frequency SEREN = 0 (in 2-wire mode) Erase Cycle Time AC test load = 50pF. Float delays are measured with 5pF AC loads. Transition is measured ±200mV from steady-state active levels. See the AT17F(A) Programming Specification for procedural information. AC Characteristics When Cascading Min DCLK to Data Float Delay DCLK to...

Figure 9-2. AC Waveforms when Cascading

Ordering Information Ordering Code Detail AT 1 7 F 1 6 A - 3 0 C U Package Device Grade Atmel Designator U = Green, Sn Lead Finish Industrial Temperature Range (-40°C to +85°C) Product Family 17F = FPGA Flash Configuration Memory Package Option Device Density Product Variation 30 = Default Value Special Pinouts A = Altera Blank = Xilinx/Atmel/Other Ordering Information Memory Size 16-Mbit Atmel Ordering Code AT17F16A-30CU AT17F16A-30JU Lead Finish 8-pad, 6.00mm x 6.00mm x 1.04mm, Leadless Array Package (LAP) Pin-compatible with 8-lead SOIC/VOIC Packages 20-lead, Plastic J-leaded Chip...

Packaging Information Side View COMMON DIMENSIONS (Unit of Measure = mm) Bottom View 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. Ni: 0.0005 to 0.015 mm Au: 0.0005 to 0.001 mm 12/22/14 TITLE Package Drawing Contact: packagedrawings@atmel.com 8CN4, 8-pad 6x6x1.04mm Body, 1.27mm pitch Leadless Array Package (LAP)

COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102mm) maximum 10/04/01 Package Drawing Contact: packagedrawings@atmel.com TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)