2108, VXI Serial Bus Simulator/Analyzer
9Pages

{{requestButtons}}

Catalog excerpts

2108, VXI Serial Bus Simulator/Analyzer - 1

Astronics Test Systems Inc. Talon Instruments™ VXI Serial Bus Emulator The Talon Instruments™ 2108 Serial Bus Simulator/Analyzer can be programmed to simulate a wide range of serial buses for both automated test and research & development environments. When used in the automated test environment, the 2108 goes beyond simple bus emulation with its unique ability to impose a range of impairments on the data, clock, and even control lines associated with the Serial Bus Under Test (SBUT) for margin/limit testing. You also receive a set of interactive tools for the development and analysis of new serial buses (or for the modification of standard buses). Product Information • Development environment GUI included The 2108 provides standard encoding and formatting schemes which allow the user to quickly emulate and analyze the most common serial buses. 2108 transmit and receive modules are coupled to the front panel via UUT I/O modules (TX and RX modules). These modules can be specified to support multiple signal types or, alternatively, one signal type such as LVDS or RS-485. Custom interconnect modules can be developed to meet emerging user physical interface requirements. • Serial bus logic analyzer application included Modular Design • 4 transmit and/or receive channels per VXI slot for analysis of serial buses up to 200 MHz and 15 V • Test/simulate transmit & receive characteristics of serial buses • Emulate SONET, T1/DS1, 422/485, USB, IEEE-1394, ethernet, custom, or modified serial buses • Dual 4 Meg ping-pong buffers for real-time operation The 2108 is a register-based VXI module which provides fast communications between the unit and the VXI controller. This allows data to be transferred in continuous mode via a 4 Meg ping-pong buffer. The 2108 baseboard houses 1-4 serial channels and associated UUT I/O interconnect modules. Each channel may be a transmitter or receiver and is addressed as an independent instrument. Adjacent transmitters and receivers may be linked and operated as bi-directional buses. Clock Recovery Clock recovery is important when serial schemes embed the master clock within the serial data stream. When there is no clock available to a serial data stream, one of two clock recovery methods are used to recover the clock in real-time from 949.859.8999; 800.722.2528; atssales@astronics.com; www.astronicstestsystems.com Copyright © 2014 Astronics Test Systems Inc. the serial data stream input to the 2108 receiver. Low Frequency Clock Recovery (LF-CR) mode uses a 6x over-sampling method to recover a clock from input data streams at transition rates up to 35 Mbps (Megabits per second). High Frequency Clock Recovery (HF-CR) mode employs a PLL to lock onto the incoming data stream for transition rates from 32 to 200 Mbps. Bi-directional Mode When 2108 receive and transmit modules are used in pairs, they are linked together and can be used in tandem for bi-directional functionality. This is important when testing a serial device which transmits data with the expectation of a response from the party receiving the data or for the simulation of multi-drop architectures. The 2108 implements this by: • Using the receiver’s ability to compare incoming data to any of up to 16 preprogrammed comparison words. • Sending a trigger signal to the linked transmitter upon receipt of data that meets specific criteria. • Sending an appropriate response message upon receipt of the trigger. • Operating in synchronization with the receiver’s clock so that the return message can be synchronized with the clock of the external device. Developer’s Toolkit The 2108 comes with a VXIplug&play compatible driv

Open the catalog to page 1
2108, VXI Serial Bus Simulator/Analyzer - 2

Astronics Test Systems Inc. Product Information Microsoft Win32® application programming interface and a Developer's Toolkit for the development of driver-compatible projects. This set of graphical utilities allows the user to configure the instrument, download and upload data, and to interactively execute test routines. The project and data files generated may be saved for download and execution by any program using tools provided by the instrument driver. In particular, the 2108 Developer's Toolkit includes the utilities needed to graphically define the 2108 "transmit" and "receive" To...

Open the catalog to page 2
2108, VXI Serial Bus Simulator/Analyzer - 3

Astronics Test Systems Inc. Product Information continued Table 1: Trinary Transmit/Receive Modes Trinary Transmit Modes Mode Description Binary plus tri-state (Note: Tri-stating may be used in combination with the other transmit modes) Binary plus user-defined state A “one” and “zero” state are defined as usual, with a third state being defined as a user-defined voltage level. Binary plus error state Mode Diagram A “one” and “zero” state are defined as usual, with a third state being defined as tri-state. This mode is useful for bi-directional serial buses. A “one” and “zero” state are...

Open the catalog to page 3
2108, VXI Serial Bus Simulator/Analyzer - 4

Astronics Test Systems Inc. Product Information Table 2: 2108 Data Formatting Parity is calculated on-the-fly for 8-bit words sent to the transmitter. Parii>Conlrol:|Res<st ^ Paty I Default Bank |A H Continue party count from ptevjous table Do not change parity count duriixi this Pre-defined custom waveform patterns of variable length for packet synchronization or inter- message gaps Sync command WPRI vRtt.A. sb«._ri_n_ WPR2 VRe(:B, 8 bits. "I_!~l_!~!_ Inter-message gaps or fixed transmitter gaps Uset defined data [4 to 4S bits) Pseudo Random Btl Sequence (4 to 6553S bit times) User defined...

Open the catalog to page 4
2108, VXI Serial Bus Simulator/Analyzer - 5

Astronics Test Systems Inc. Product Information continued for sequence size, available words, step editing, and subroutine activation. Serial Logic Analyzer A Serial Logic Analyzer application is included which is used to view recorded data. It allows the user to search for events by trigger counts or by pattern. You may define templates to align, read, and display data streams. This tool can be used as a design and debug tool for simulating new designs of custom or modified buses in the development lab. Margin Testing Every communications system operates within a certain margin from the...

Open the catalog to page 5

All Astronics Test Systems catalogs and technical brochures

  1. 1264c

    2 Pages

  2. 4024h

    1 Pages

  3. Option 01T

    2 Pages

  4. 1256L

    2 Pages

  5. 1260-101

    2 Pages

  6. 1260-100

    2 Pages

  7. 1260-152/172

    3 Pages

  8. 1260-120

    3 Pages

  9. 1260-120

    3 Pages

  10. 1260-150

    3 Pages

  11. 1260-138A

    3 Pages

  12. 1260-134

    2 Pages

  13. 1260-145A-G

    3 Pages

  14. 1260-116

    2 Pages

  15. 3172

    6 Pages

  16. 3152B

    6 Pages

  17. 3151B

    5 Pages

  18. 3164_2_0

    3 Pages

  19. 3156c

    5 Pages

  20. 313A

    1 Pages

  21. 6084-2105

    2 Pages

  22. PXIe-1803

    4 Pages

  23. PXIe-6943

    6 Pages

  24. VX407C

    2 Pages

  25. VX405C

    2 Pages

  26. 203PC-1, 2

    3 Pages

  27. 1257A

    10 Pages

  28. 1263HPf

    2 Pages

  29. T940

    8 Pages

  30. 1261B-S-2378

    2 Pages

  31. 1261B linear

    3 Pages

  32. 1261B

    5 Pages

  33. 1260-x153

    2 Pages

  34. 1260-x121

    2 Pages

  35. 1260-1114

    2 Pages

  36. 1260-700

    2 Pages

  37. 1260-155

    2 Pages

  38. 1260-115

    2 Pages

  39. 1260-114

    3 Pages

  40. 1260-100

    2 Pages

  41. 1260-88

    2 Pages

  42. 1260-75

    2 Pages

  43. 1260-58

    2 Pages

  44. 1260-54

    2 Pages

  45. 1260-51

    2 Pages

  46. 1260-16

    2 Pages

  47. 1260-14

    2 Pages

  48. 1260-00C

    3 Pages

  49. 1255A

    2 Pages