*mydirectindustry

Catalogs
Analog Devices
AD9680: 14-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter

AD9680: 14-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter

Product catalog summary

Introduction
The AD9680 is a dual, 14-bit, 1 GSPS analog-to-digital converter (ADC) designed by Analog Devices. It features a multistage, differential pipelined architecture with integrated output error correction logic, optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power consumption.

Key Features

JESD204B (Subclass 1) coded serial digital outputs.
1.65 W total power per channel at 1 GSPS.
SFDR of 85 dBFS at 340 MHz and 80 dBFS at 1 GHz.
SNR of 65.3 dBFS at 340 MHz and 61.4 dBFS at 1 GHz.
ENOB of 10.8 bits at 10 MHz.
Flexible input range and termination impedance.
2 GHz usable analog input full power bandwidth.
95 dB channel isolation/crosstalk.
Integrated wideband digital processors per channel.

Applications

Communications, including 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE.
General-purpose software radios and ultrawideband satellite receivers.
Instrumentation, radars, and signals intelligence (SIGINT).

Specifications

DC Specifications: Includes resolution of 14 bits, offset error, gain error, and power supply requirements.
AC Specifications: Details on noise density, SNR, SINAD, ENOB, SFDR, and intermodulation distortion.
Digital Specifications: Covers the JESD204B interface and digital output configurations.

Functional Overview
The AD9680 supports IF sampling of signals up to 2 GHz with buffered inputs and programmable input termination. It includes four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks for multiband receivers. The device also features a flexible serial port interface (SPI) for controlling various product features and functions.

Power and Thermal Management

Flexible power-down options for significant power savings.
Specified over the −40°C to +85°C industrial temperature range.

Conclusion
The AD9680 is a versatile ADC suitable for a wide range of high-speed data conversion applications, offering high performance, flexibility, and ease of integration into various systems.

Specifications

Clock Inputs: The device supports LVDS/LVPECL logic with a differential input voltage range of 600 to 1800 mV p-p and a common-mode voltage of 0.85 V.
SYSREF Inputs: Similar logic compliance as clock inputs with a differential input voltage range of 400 to 1800 mV p-p and a common-mode voltage range of 0.6 to 2.0 V.
Logic Inputs/Outputs: Compliant with CMOS logic, with specific voltage levels for logic 1 and 0 based on SPIVDD.
Digital Outputs: CML logic with a differential output voltage range of 360 to 770 mV p-p.
Switching Specifications: The clock rate ranges from 0.3 to 4 GHz, with a maximum sample rate of 1000 MSPS and a minimum of 300 MSPS.
Timing Specifications: Detailed timing requirements for CLK+ to SYSREF+ and SPI timing are provided.

Absolute Maximum Ratings
The document outlines the maximum voltage ratings for various power supplies and environmental conditions, including operating and storage temperature ranges.

Thermal Characteristics
Provides thermal resistance values (θJA, θJB, θJC) for different PCB types and airflow conditions, emphasizing the importance of thermal management.

Pin Configuration
A detailed description of the pin functions, including power supplies, analog inputs, digital inputs/outputs, and control pins.

Performance Characteristics
Includes FFT plots and performance metrics such as SNR, SFDR, and power dissipation across different conditions and configurations.

Figures and Diagrams
The document contains various figures illustrating timing diagrams, pin configurations, and equivalent circuits for different inputs and outputs.

Theory of Operation
The AD9680 is a dual-channel ADC designed for sampling wide bandwidth analog signals up to 2 GHz. It features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC supports wide bandwidth inputs with user-selectable input ranges and includes an integrated voltage reference. It simplifies AGC functions in communication receivers with a programmable threshold detector for monitoring incoming signal power.

ADC Architecture
The AD9680 architecture includes an input buffered pipelined ADC with a default termination impedance of 400 Ω. The input buffer is optimized for high linearity, low noise, and low power, providing a linear high input impedance and reducing kickback from the ADC. The pipelined architecture allows simultaneous operation of different stages with new and preceding samples.

Analog Input Considerations
The AD9680's analog input is a differential buffer with an internal common-mode voltage of 2.05 V. For optimal performance, the source impedances driving the inputs must be matched. The ADC's span is programmable from 1.46 V p-p to 1.94 V p-p differential, with 1.70 V p-p as the default. Differential transformer coupling is recommended for applications prioritizing SNR and SFDR.

Voltage Reference
The AD9680 includes a stable 1.0 V internal voltage reference, adjustable via the SPI port. An external reference can be used to enhance gain accuracy or improve thermal drift characteristics.

Clock Input Considerations
For optimal performance, the AD9680 sample clock inputs should be driven with a differential signal, typically ac-coupled via a transformer or clock drivers. The ADC includes an input clock divider with selectable ratios and can be synchronized using the external SYSREF± input.

Power-Down/Standby Mode
The AD9680 features a PDWN/STBY pin for configuring the device in power-down or standby mode, with the default operation being power-down.

Power Management and JESD204B Link
The AD9680 allows for power-down via registers 0x03F and 0x040. In standby mode, the JESD204B link remains active, transmitting zeroes unless configured to send /K/ characters using Register 0x571, Bit 7.

Temperature Diode
The AD9680 includes a diode-based temperature sensor for monitoring die temperature. The diode voltage can be output to the FD_A pin, enabled via Register 0x028, Bit 0, with Channel A selected in the device index register (0x008). Configuration details are in Table 29.

ADC Overrange and Fast Detect
The AD9680 features fast detect circuitry to monitor input thresholds and assert FD_A and FD_B pins. Overrange indicators are embedded in the JESD204B link and recorded in Register 0x563. Fast detect thresholds are programmable, with upper and lower thresholds set in Registers 0x247-0x24A, and dwell time in Registers 0x24B-0x24C.

Digital Downconverter (DDC)
The AD9680 includes four DDCs for filtering and data rate reduction. Each DDC can handle real or complex inputs and outputs, controlled by registers 0x311, 0x331, 0x351, and 0x371. The DDCs include stages for frequency translation, filtering, gain, and complex-to-real conversion. Configuration details are provided in the document, including decimation ratios and synchronization requirements.

Figures and Tables
The document includes figures illustrating temperature diode voltage response, threshold settings for FD signals, and DDC block diagrams. Tables provide detailed configuration options for DDC samples and decimation ratios.

DDC Samples and Decimation
The document outlines various configurations for DDC samples with different chip decimation ratios (DCM). It explains how different combinations of half-band FIR filters (HB1, HB2, HB3, HB4) are used depending on the decimation ratio, affecting the output sample rates for real and complex signals.

Frequency Translation
Frequency translation is achieved using a 12-bit complex numerically controlled oscillator (NCO) and a digital quadrature mixer. The document describes four IF modes: Variable IF, 0 Hz IF (ZIF), fS/4 Hz IF, and Test mode. Each mode has specific configurations for enabling or bypassing mixers and NCOs.

NCO and Mixer Loss
The document details the signal loss introduced during frequency translation, recommending compensatory gain adjustments. It also discusses the spurious-free dynamic range (SFDR) performance of the NCO.

FIR Filters
The AD9680 includes four sets of decimate-by-2, low-pass, half-band FIR filters. These filters are used to lower the sample rate and provide alias rejection. The document provides detailed coefficients and responses for each filter (HB1, HB2, HB3, HB4), highlighting their role in signal processing.

NCO Setup and Synchronization
Instructions are provided for setting up the NCO frequency tuning word (FTW) and phase offset word (POW). Synchronization methods using SPI or SYSREF± pin are explained to ensure proper operation across multiple channels or chips.

Recommendations
The document recommends enabling additional gain to compensate for signal loss during mixing and provides guidelines for configuring the DDC control registers to achieve desired decimation and filtering outcomes.

HB1 Filter Response
The document discusses the HB1 filter, highlighting its coefficients and response characteristics. Figure 57 illustrates the filter's response, showing the magnitude in decibels against normalized frequency.

DDC Gain Stage
Each Digital Downconverter (DDC) includes a gain stage with selectable gains of 0 dB or 6 dB. For real input signals mixed to baseband, enabling 6 dB gain is recommended to optimize dynamic range. For complex signals, additional gain is optional to compensate for low signal strengths.

DDC Complex to Real Conversion
The DDC features a complex to real conversion block, utilizing the HB1 FIR filter and an fS/4 complex mixer. This process upconverts the signal, discarding the Q portion post-conversion.

DDC Example Configurations
Table 22 provides register settings for various DDC configurations, detailing chip application layers, decimation ratios, input/output types, bandwidths, and required virtual converters. Configurations range from single to multiple DDCs with complex or real outputs.

Digital Outputs and JESD204B Interface
The AD9680 digital outputs adhere to the JESD204B standard, facilitating high-speed serial data transmission up to 12.5 Gbps. This interface reduces board area and supports smaller package sizes. The JESD204B link parameters include lanes, converters, octets, and control bits, ensuring synchronization and data integrity.

JESD204B Link Establishment
The link establishment involves synchronization, lane alignment, and error correction. The AD9680 supports various configurations, including combining converter outputs onto single lanes, with data framed and encoded using 8B/10B encoding.

Code Group Synchronization (CGS) and SYNCINB±
The CGS process allows the JESD204B receiver to find boundaries between 10-bit symbols in the data stream. During CGS, the transmitter sends /K28.5/ characters, and the receiver uses clock and data recovery techniques to locate these characters. Synchronization is requested by asserting the SYNCINB± pin low, and once synchronized, the receiver waits for four consecutive /K/ symbols before deasserting SYNCINB±. The SYNCINB± pin can be controlled by SPI and operates in differential LVDS mode by default.

Initial Lane Alignment Sequence (ILAS)
Following CGS, ILAS begins on the next LMFC boundary and consists of four multiframes. Each multiframe starts with an /R/ character and ends with an /A/ character. The sequence includes ramp data and link configuration data, and is never scrambled.

User Data and Error Detection
After ILAS, user data is sent. Frame and multiframe synchronization is monitored by replacing certain characters with /F/ or /A/ alignment characters under specific conditions. The scrambling operation is enabled by default but can be disabled via SPI.

8B/10B Encoder
This encoder converts 8-bit octets into 10-bit symbols, ensuring DC balance. Control characters are inserted as needed, and the encoder can be configured via SPI for troubleshooting.

Physical Layer (Driver) Outputs
The AD9680's physical layer includes drivers with dynamic 100 Ω internal termination. Differential termination is recommended, and the digital outputs can interface with custom ASICs and FPGA receivers. De-emphasis can be used to meet eye diagram masks under certain conditions.

JESD204B Tx Converter Mapping
The AD9680 supports different chip operating modes, treating each sample stream as originating from separate virtual converters. The JESD204B Tx block supports up to four DDC blocks, with configurations for real or complex data outputs.

Configuring the JESD204B Link
The AD9680 offers a straightforward setup for the JESD204B link through a quick configuration register. Key parameters include the number of lanes, converters, and octets per frame. The maximum lane rate is 12.5 Gbps, and configurations must ensure the serial line rate is within the supported range.

JESD204B Output Configurations
The AD9680 supports various JESD204B output configurations, which are determined by parameters such as the number of virtual converters (M), the quick configuration code, and the serial line rate. The document specifies valid configurations for different values of F and K, emphasizing that K values must be divisible by 4.

Example Configurations

Full Bandwidth Mode: Utilizes two 14-bit converters at 1000 MSPS with no decimation, requiring two virtual converters and supporting configurations with N' = 16 bits and L = 4.
ADC with DDC Option: Involves two ADCs and four DDCs with a decimation ratio of 16, requiring eight virtual converters and supporting configurations with N' = 16 bits and L = 1 or 2.

Serial Port Interface (SPI)
The AD9680 features an SPI for configuring the converter, offering flexibility for various applications. The SPI uses three pins: SCLK, SDIO, and CSB, and supports both read and write operations. The document advises against activating the SPI during critical sampling periods to avoid performance degradation.

Memory Map
The memory map is divided into sections for SPI registers, ADC function registers, DDC function registers, and digital outputs/test modes. Each register has a default value, and the document provides guidelines for writing to these registers, including handling open and reserved locations.

SPI Accessible Features
The SPI allows access to features such as power modes, clock settings, decimation filters, test modes, and SERDES output setup. The document emphasizes the importance of adhering to default values and logic level terminology when configuring the device.

Conclusion
The AD9680 data sheet provides comprehensive information on configuring and operating the ADC, with detailed examples and guidelines for using the JESD204B interface and SPI. It is essential for users to follow the specified configurations and operational recommendations to ensure optimal performance.

Specifications

JESD204B Configuration: The AD9680 supports various configurations for scrambling, lane numbers, octets per frame, frames per multiframe, converters per link, control bits per sample, and ADC resolution. Specific register addresses and default values are provided for each configuration.
Power Supply: The AD9680 requires seven power supplies: AVDD1 (1.25 V), AVDD2 (2.5 V), AVDD3 (3.3 V), AVDD1_SR (1.25 V), DVDD (1.25 V), DRVDD (1.25 V), and SPIVDD (1.25 V). Recommendations for power supply design include using switching regulators and low dropout (LDO) regulators for optimal efficiency and noise performance.
Thermal Management: The exposed pad on the ADC must be connected to AGND for optimal thermal and electrical performance. A continuous copper plane with several vias is recommended for heat dissipation.

Procedures

Power Supply Recommendations: Use ADP2164 and ADP2370 switching regulators to convert input rails to intermediate rails, followed by LDO regulators for post-regulation. Decoupling capacitors should be used to minimize noise.
PCB Layout: The document provides guidelines for PCB layout, including the use of a silkscreen to partition the copper plane for better adhesion during the reflow process.

Standards and Compliance

The AD9680 is compliant with JEDEC standards MO-220-WMMD for packaging.

Recommendations

For applications requiring high power efficiency and low noise, follow the recommended power supply scheme.
Ensure proper connection of the exposed pad to AGND for thermal management.

Ordering Information
The document lists available models, temperature ranges, and package descriptions for ordering the AD9680.

Catalog excerpts

AD9680: 14-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter-1

14-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter AD9680 Data Sheet FEATURES VIN+B VIN–B CONTROL REGISTERS FAST DETECT CLOCK GENERATION DRGND DGND SDIO SCLK CSB PDWN/ STBY APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers JESD204B HIGH SPEED SERIALIZER + Tx OUTPUTS BUFFER VIN+A VIN–A FAST DETECT JESD204B (Subclass 1) coded serial digital outputs 1.65 W total power per channel at 1 GSPS (default settings) SFDR = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz SNR = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS), 61.4 dBFS at 1 GHz ENOB = 10.8 bits at 10 MHz DNL = ±0.5 LSB INL = ±2.5 LSB Noise density = −154 dBFS/Hz at 1 GSPS 1.25 V, 2.5 V, and 3.3 V dc supply operation No missing codes Internal ADC voltage reference Flexible input range and termination impedance 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal) 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential 2 GHz usable analog input full power bandwidth 95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated wideband digital processors per channel 12-bit NCO, up to 4 cascaded half-band filters Differential clock input Integer clock divide by −1, 2, 4, or 8 Flexible JESD204B lane configurations Small signal dither Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm × 9 mm 64-lead LFCSP. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

Open the catalog to page 1

AD9680: 14-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter-2

Data Sheet REVISION HISTORY 5/14—Revision 0: Initial Version

Open the catalog to page 2

AD9680: 14-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter-3

Data Sheet GENERAL DESCRIPTION The AD9680 is a dual, 14-bit, 1 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sampleand-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting...

Open the catalog to page 3

AD9680: 14-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter-4

Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (1000 MSPS), 1.7 V p-p full-scale differential input, 1.0 V internal reference, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Non-Linearity (INL) TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Voltage INPUT-REFERRED...

Open the catalog to page 4

AD9680: 14-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter-5

Data Sheet AC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, 1.7 V p-p full-scale differential input, 1.0 V internal reference, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted. Table 2. Parameter 1 ANALOG INPUT FULL SCALE NOISE DENSITY 2 SIGNAL-TO-NOISE RATIO (SNR) 3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz SNR AND DISTORTION RATIO (SINAD)3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN =...

Open the catalog to page 5

AD9680: 14-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter-6

Data Sheet Parameter 1 fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = −7 dBFS fIN1 = 185 MHz, fIN2 = 188 MHz fIN1 = 338 MHz, fIN2 = 341 MHz CROSSTALK 4 FULL POWER BANDWIDTH 5 Unit dBFS dBFS dBFS dBFS dBFS dB GHz See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Noise density is measured at a low analog input frequency (30 MHz). 3 See Table 9 for recommended settings for full scale voltage and buffer current setting 4 Crosstalk is measured...

Open the catalog to page 6

AD9680: 14-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter-7

Data Sheet Parameter DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 3) Logic Compliance Differential Output Voltage Output Common-Mode Voltage (VCM) AC Coupled Short-Circuit Current (IDshort) Differential Return Loss (RLDIFF) 1 Common-Mode Return Loss (RLCM) 1 Differential Termination Impedance 1 Differential and common-mode return loss is measured from 100 MHz to 0.75 MHz × baud rate. SWITCHING SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, 1.7 V p-p full-scale differential input, 1.0 V internal...

Open the catalog to page 7

AD9680: 14-Bit, 1 GSPS JESD204B, Dual Analog-to-Digital Converter-8

Data Sheet TIMING SPECIFICATIONS Table 5. Parameter CLK+ to SYSREF+ TIMING REQUIREMENTS tSU_SR tH_SR SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO Test Conditions/Comments See Figure 3 Device clock to SYSREF+ setup time Device clock to SYSREF+ hold time See Figure 4 Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK must be in a logic high state Minimum period that SCLK must be in a logic low state Time required...

Open the catalog to page 8