*mydirectindustry

Catalogs
Analog Devices
AD9625: 12-Bit 2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converted

AD9625: 12-Bit 2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converted

Product catalog summary

Overview: The AD9625 is a high-performance 12-bit analog-to-digital converter (ADC) with a sampling rate of up to 2.0 GSPS, designed for applications requiring wide bandwidth and high linearity, such as spectrum analyzers, radar, and military communications.

Key Features:

12-bit resolution with no missing codes.
Sampling rate of 2.0 GSPS.
Signal-to-Noise Ratio (SNR) of 59 dBFS for input frequencies up to 1 GHz.
Spurious-Free Dynamic Range (SFDR) of 80 dBc for input frequencies up to 1 GHz.
Power consumption of 3.5 W at 2.0 GSPS.
Supports differential analog and clock inputs.
High-speed JESD204B serial output with flexible lane configurations.
Built-in digital test patterns and selectable digital output modes.

Applications: Suitable for spectrum analyzers, military communications, radar systems, high-performance digital storage oscilloscopes, and electronic surveillance.

Specifications:

DC Specifications: Offset error of ±0.5 LSB, gain error of ±8% FSR, differential input voltage range of 1.1 V p-p.
AC Specifications: Noise floor of -149.5 dBFS/Hz, effective number of bits (ENOB) of 9.4 bits at 100 MHz input frequency.
Digital Specifications: Supports differential input voltages for clock and SYSREF inputs, with logic compliance for CMOS and LVDS.
Switching Specifications: Maximum clock rate of 2000 MSPS, with a clock pulse width duty cycle of 50% ± 5%.

Functional Description: Features a monolithic sampling architecture, supporting wide bandwidth analog signals up to the second Nyquist zone, and includes a JESD204B-based high-speed serialized output.

Product Highlights: Offers exceptional SFDR in high sample rate applications, flexible digital data output formats, and a control path SPI interface for various product features and functions.

Pin Configuration: Detailed pin configuration and function descriptions, including key pins for clock input, differential analog input, and various power and ground pins.

Interface and Timing: Illustrates the timing relationship between CLK input and DOUT, highlighting setup and hold times for SYSREF signals.

Recommendations: Advises on proper grounding and power supply connections to ensure optimal performance and reliability.

Performance Characteristics:

FFT Plots: Demonstrates performance at 2.0 GSPS with various input frequencies, highlighting SFDR and SNR values.
SNR/SFDR vs. Amplitude: Shows the relationship between signal amplitude and performance metrics.
Current and Power vs. Sample Rate: Illustrates power consumption across different sample rates.

Theory of Operation:

ADC Architecture: Utilizes a pipelined structure with flash ADCs and MDACs for efficient sampling and error correction.
Fast Detect: Provides rapid detection of input signal levels to prevent ADC overload.
Gain Threshold Operation: Uses thresholds to manage calibration updates based on signal amplitude.

Test Modes: Includes various output test modes accessible via SPI registers, allowing for flexible testing and calibration.

Digital Downconverters (DDC):

Architecture: Features two DDCs with independent frequency synthesizers and mixers, supporting high and low bandwidth modes.
Decimation and Filtering: Employs decimate-by-8 polyphase filters for efficient bandwidth management and noise reduction.

Equivalent Test Circuits: Provides circuit diagrams for analog input, SCLK, temperature sensor, clock input, and CSB input, aiding in system integration and testing.

Analog Input Considerations: Recommends series resistors to minimize bandwidth peaking and kickback from the ADC sampling capacitor.

Clock Input Considerations: Requires a differential signal for optimal performance, with a formula provided to calculate SNR degradation due to aperture jitter.

Calibration: Requires a calibration cycle at startup and every 24 hours, involving specific register writes and mode maintenance.

Digital Outputs and JESD204B Interface: Complies with the JESD204B standard, supporting serial interface speeds up to 6.5 Gbps, with up to eight output lanes and 8-bit/10-bit encoding.

JESD204B Link Establishment: Details the process of code group synchronization, initial lane alignment sequence, and data streaming.

8-Bit/10-Bit Encoder: Converts 8-bit octets into 10-bit characters, ensuring DC balance in the signal.

DC-Coupled Digital Output Termination: Discusses the importance of proper termination and trace routing to avoid timing errors.

De-Emphasis: Used to meet the receiver eye diagram mask when interconnect insertion loss is high, but generally disabled to conserve power.

Control Characters in JESD204B: Lists control characters used in JESD204B, including their 8-bit and 10-bit values, and their functions.

JESD204B Mode of Operation: Various configurations for JESD204B are detailed, specifying lanes, octets per frame, sample clock rates, and lane rates.

Logical Lane Mapping: Provides a mapping of logical lanes for different configurations.

Physical Layer Output: Figures illustrate the recovered data eye, bathtub plot, and time interval histogram error for JESD204B output at 6.25 Gbps.

Scrambler and Tail Bits: Controlled via specific registers, enabling or disabling these features as needed.

DDC Modes: Supports single and dual digital downconverter (DDC) modes, allowing for bandwidth reduction when full bandwidth is not required.

Checksum and Encoder Control: The checksum is used during the initial lane alignment sequence, and the 8-bit/10-bit encoder is controlled through specific registers.

Initial Lane Alignment Sequence (ILAS): Supports multiple ILAS modes, with the ability to repeat the sequence a specified number of times.

Lane Synchronization: Controlled via a specific register, enabling or disabling this feature as needed.

ADC Output Control Bits: Control bits can be used for overrange and time-stamped SYSREF control, with various test patterns available for interface testing.

JESD204B Application Layers: Outlines different application layer modes, including single and dual DDC modes with varying bandwidths, and fS × 2, fS × 4, fS × 8 modes for rate conversion.

Frame Alignment Character Insertion (FACI): Can be enabled or disabled via the register map, primarily used for testing purposes.

Thermal Considerations: Adequate airflow or a heat sink is crucial to prevent the case temperature from exceeding 85°C.

Power Supply Considerations: Requires two power supplies: 1.3 V for AVDD1, DVDD1, DRVDD1 and 2.5 V for AVDD2, DVDD2, DRVDD2, with recommendations for using the ADP2386 switching regulator.

Serial Port Interface (SPI): Allows configuration of the ADC through a structured register space, supporting both MSB first and LSB first data modes.

Memory Map: Divided into sections for chip configuration, transfer register, and ADC functions, with default values provided for each register.

Registers Overview: Details several registers, including the SPI Configuration Register, Chip ID Register, Chip Grade Register, Power Control Mode Register, PLL Status Register, ADC Test Control Register, Data Path Customer Offset Register, Output Mode Register, and Serializer Output Adjust Register.

User Test Pattern Registers: Registers 0x01E, 0x01F, and 0x020 are used for User Test Patterns 3 and 4.

Synthesizer PLL Control Register (0x021): Controls power-down of VCO LDO and has reserved bits for future use.

ADC Analog Input Control Register (0x02C): Allows setting functions on the VMON pin, enabling external reference application.

SYSREF Control Register (0x03A): Manages SYSREF status, transition selection, capture edge, and mode.

Fast Detect Control Registers: Registers 0x045 to 0x04C manage fast detect features, including thresholds and dwell time counters.

JESD204B Quick Configuration Register (0x05E): Provides quick configuration options for JESD204B serial interface.

JESD204B Link Control Registers: Registers 0x05F to 0x063 control various JESD204B link features.

JESD204B Configuration Registers: Registers 0x064 to 0x067 manage device, bank, and lane identification numbers for JESD204B.

ADC Calibration Procedure: At startup, overwrite the default value in Register 0x12A[7:0] with 0x03 to initiate ADC calibration, and repeat this cycle every 24 hours.

DIVCLK± Output Control (Register 0x120): Controls DIVCLK± output, output termination, and differential swing.

DDC Gain Control Registers: Configure polyphase gain for decimate by 2 and decimate by 8 modes.

DDC Phase Increment Registers: Control NCO phase increment, with output frequency calculated using a specific formula.

Outline Dimensions: Available in a 196-Ball Ball Grid Array, thermally enhanced package, compliant with JEDEC standards.

Ordering Information: Includes various models and evaluation boards with specific operating temperature ranges.

Catalog excerpts

AD9625: 12-Bit 2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converted-1

Data Sheet FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD DRGND DIGITAL INTERFACE AND CONTROL RBIAS CONTROL REGISTERS SYSREF± CLK± CLOCK MANAGEMENT CMOS DIGITAL INPUT/OUTPUT CMOS DIGITAL INPUT/ OUTPUT LVDS DIGITAL INPUT/ OUTPUT 12-bit 2.0 GSPS ADC, no missing codes SFDR = 80 dBc, AIN up to 1 GHz at −1 dBFS, 2.0 GSPS SFDR = 76 dBc, AIN up to 1.8 GHz at −1 dBFS, 2.0 GSPS SNR = 59 dBFS, AIN up to 1 GHz at −1 dBFS, 2.0 GSPS SNR = 58 dBFS, AIN up to 1.8 GHz at −1 dBFS, 2.0 GSPS Noise floor = −149.5 dBFS/Hz at 2.0 GSPS Power consumption: 3.5 W at 2.0 GSPS Differential analog input: 1.1 V p-p Differential clock input High speed 6- or 8-lane JESD204B serial output Subclass 1: 5.0 Gbps at 2.0 GSPS Two independent decimate by 8 or decimate by 16 filters with 10-bit NCOs Supply voltages: 1.3 V, 2.5 V Serial port control Flexible digital output modes Built-in selectable digital test patterns APPLICATIONS Spectrum analyzers Military communications Radar High performance digital storage oscilloscopes Active jamming/antijamming Electronic surveillance and countermeasures GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9625 is a 12-bit monolithic sampling analog-to-digital converter (ADC) that operates at conversion rates of up to 2.0 giga samples per second (GSPS). This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9625 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and jamming/antijamming measures. High performance: exceptional SFDR in high sample rate applications, direct RF sampling, and on-chip reference. Flexible digital data output formats based on the JESD204B specification. Control path SPI interface port that supports various product features and functions, such as data formatting, gain, and offset calibration values. The analog input, clock, and SYSREF± signals are differential inputs. The JESD204B-based high speed serialized output is configurable in a variety of one-, two-, four-, six-, or eight-lane configurations. The product is specified over the industrial temperature range of −40°C to +85°C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. Technical Support

Open the catalog to page 1

AD9625: 12-Bit 2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converted-2

Data Sheet REVISION HISTORY 5/14—Revision 0: Initial Version

Open the catalog to page 2

AD9625: 12-Bit 2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converted-3

Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal reference, AIN = −1.0 dBFS, default SPI settings, dc-coupled output data, unless otherwise noted. Table 1. Parameter SPEED GRADE RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) ANALOG INPUTS Differential Input Voltage Range Resistance Capacitance Internal Common-Mode Voltage (VCM) Analog Full Power Bandwidth Input Referred Noise POWER SUPPLIES AVDD1 AVDD2 DRVDD1 DRVDD2...

Open the catalog to page 3

AD9625: 12-Bit 2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converted-4

Data Sheet AC SPECIFICATIONS AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling, 1.2 V internal reference, AIN = −1.0 dBFS, sample clock input = 1.65 V p-p differential, default SPI settings, unless otherwise noted. Table 2. Parameter SPEED GRADE ANALOG INPUT NOISE DENSITY SIGNAL-TO-NOISE RATIO (SNR) fIN = 100 MHz fIN = 500 MHz fIN = 1000 MHz fIN = 1800 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 100 MHz fIN = 500 MHz fIN = 1000 MHz fIN = 1800 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 100 MHz fIN = 500 MHz fIN = 1000 MHz fIN = 1800 MHz SPURIOUS FREE...

Open the catalog to page 4

AD9625: 12-Bit 2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converted-5

Data Sheet Parameter Input Resistance (Differential) Input Capacitance LOGIC INPUTS (SDIO, SCLK, CSB) Logic Compliance Voltage Logic 1 Logic 0 Input Resistance Input Capacitance SYNCB+/SYNCB− INPUT (SYNCINB+, SYNCINB−) Logic Compliance Input Voltage Differential Common Mode Input Resistance (Differential) Input Capacitance LOGIC OUTPUT (SDIO) Logic Compliance Voltage Logic 1 (IOH = 800 μA) Logic 0 (IOL = 50 μA) DIGITAL OUTPUTS (SERDOUT[x]±) Compliance Output Voltage Differential Offset Differential Return Loss (RLDIFF) 1 Common-Mode Return Loss (RLCM)1 Differential Termination Impedance RESET...

Open the catalog to page 5

AD9625: 12-Bit 2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converted-6

Data Sheet SWITCHING SPECIFICATIONS AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal reference, AIN = −1.0 dBFS, default SPI settings, unless otherwise noted. Table 4. Parameter CLOCK (CLK±) Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High Clock Pulse Width Low SYSREF (SYSREF±) 2 Setup Time (tSU_SR) Hold Time (tH_SR) FAST DETECT OUTPUT (FD) Latency OUTPUT PARAMETERS (SERDOUT[x]±) Rise Time Fall Time Pipeline Latency APERTURE Delay Uncertainty (Jitter) Out-of-Range Recovery Time 1 2 Test Conditions/Comments Full Full Full...

Open the catalog to page 6

AD9625: 12-Bit 2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converted-7

Data Sheet Timing Diagrams CLK– CLK+ SYSREF– SYSREF+ Figure 2. SYSREF± Setup and Hold Timing tDS SDIO DON’T CARE DON’T CARE DON’T CARE Figure 3. Serial Port Interface Timing Diagram (MSB First) JESD204B INTERFACE M = 1; L = 8; N = 12; N' = 16; CF = 0; CS = 0; CS = 0...4; K = 32; HD = 1; F = 1 500ps MIN (2.0GHz) CLK+ (ENCODE CLOCK) SAMPLE N [3:0], CCCC LANE B± @ 5.0Gbps Figure 4. CLK Input and DOUT Timing Relationship (Generic Eight-Lane Mode) Rev. 0 | Page 7 of 56 SAMPLE N + 3 [3:0], CCCC LANE H± @ 5.0Gbps SAMPLE N + 2 [3:0], CCCC LANE F± @ 5.0Gbps SAMPLE N + 1 [3:0], CCCC LANE D± @ 5.0Gbps SCLK...

Open the catalog to page 7