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AD73311: Low Cost, Low Power CMOS General Purpose Analog Front End Data Sheet

AD73311: Low Cost, Low Power CMOS General Purpose Analog Front End Data Sheet

Product catalog summary

Overview: The AD73311 is a cost-effective, low-power CMOS analog front end designed for applications like speech processing, telephony, and data communications. It features 16-bit A/D and D/A converters with programmable sample rates and gains.

Functional Block Diagram: Key components include a 1-bit DAC, reference, serial I/O port, interpolator, decimator, low-pass filters, programmable gain amplifiers, and sigma-delta modulators.

Key Features:

16-bit A/D and D/A converters
Programmable sample rates and gains
75 dB ADC SNR and 70 dB DAC SNR
64 kS/s maximum sample rate
Low group delay
Single supply operation (+2.7 V to +5.5 V)
50 mW max power consumption at 2.7 V
On-chip reference
20-lead SOIC/SSOP package

Applications: Suitable for general-purpose analog I/O, speech processing, cordless communications, telephony, active sound control, and data communications.

Specifications:

Reference: REFCAP voltage is 1.2 V with a typical output impedance of 68 Ω.
ADC: Maximum input range is 1.578 V p-p, with a nominal reference level of 1.0954 V p-p. SNR is 70 dB over a 300 Hz to 3.4 kHz range.
DAC: Maximum voltage output swing is 1.578 V p-p single-ended, with a nominal swing of 1.0954 V p-p. SNR is 62.5 dB over a 300 Hz to 3.4 kHz range.
Power Supply: Operates with AVDD1, AVDD2, and DVDD ranging from 2.7 V to 3.3 V.

Performance: Exhibits low total harmonic distortion and intermodulation distortion, with excellent crosstalk and power supply rejection characteristics.

Timing Characteristics: The MCLK period is a minimum of 61 ns, with specific timing requirements for serial port operations.

Figures and Tables: Includes figures illustrating S/(N+D) vs. VIN for both ADC and DAC at different voltages, and tables summarizing current consumption under various conditions.

Absolute Maximum Ratings: Specifies voltage and temperature limits, including:

AVDD, DVDD to GND: -0.3 V to +7 V
Operating Temperature Range: -40°C to +85°C
Storage Temperature Range: -65°C to +150°C
Maximum Junction Temperature: +150°C

Exceeding these ratings may cause permanent damage.

Ordering Guide: Lists available models, temperature ranges, package options, and evaluation board details.

Pin Configuration: Describes the function of each pin, including VOUTP/VOUTN (analog outputs) and VINP/VINN (analog inputs).

Terminology: Defines key terms such as absolute gain, crosstalk, gain tracking error, group delay, and intermodulation distortion.

Functional Description:

Encoder Channel: Includes a programmable gain amplifier and sigma-delta ADC.
ADC: Uses a sigma-delta modulator and digital decimation filter for high-resolution output.
Decimation Filter: Reduces sampling rate and increases resolution.

ESD Sensitivity: The device is sensitive to electrostatic discharge, requiring proper precautions.

Channel Overview: The decoder channel includes a digital interpolator, sigma-delta modulator, single-bit DAC, analog smoothing filter, and programmable gain amplifier.

DAC Coding: Utilizes a two's complement format.

Interpolation Filter: A sinc-cubed digital filter up-samples input words, with an option to bypass for minimum group delay.

Analog Smoothing Filter & PGA: Filters DAC output and adjusts output levels.

Differential Output Amplifiers: Provides differential analog output, with muting capability.

Voltage Reference: A bandgap reference provides a low noise, temperature-compensated reference.

Serial Port (SPORT): A bidirectional synchronous serial port compatible with DSPs, supporting multiple operation modes.

Master Clock Divider: Programmable to divide an external master clock, affecting sampling and serial clock rates.

Operation: The device can be reset via a pin or control register, with power management for selective enabling of functional blocks.

Operating Modes: Five modes are available, including diagnostic and general-purpose modes.

Control Registers: Used to configure various parameters, including clock rates and power management.

Sampling and Decimation: Explains achieving an 8 kHz sampling rate from a 64 kHz sample rate through decimation.

Group Delay: Calculated for both decimator and interpolator, emphasizing the importance of considering the final filter's group delay.

Design Considerations: Recommendations for analog input, including using high-quality dielectric capacitors for antialiasing filters.

Digital Interfacing: Designed to interface with common DSPs, detailing connections for specific DSPs.

Grounding and Layout: Proper grounding and layout are crucial for minimizing noise.

DSP Programming Considerations: Key settings for DSP SPORT configuration and programming sequence for operating a single codec in data mode.

Programming a Single AD73311 for Mixed Mode Operation: Steps to program a single codec for mixed mode operation, including setting SCLK and sample rate.

Configuring a Cascade of Two AD73311s: Describes setting up two codecs in cascade for data and mixed mode operations.

Key Notes: Highlights important considerations for data output, control word writes, and cascade configurations.

Catalog excerpts

AD73311: Low Cost, Low Power CMOS General Purpose Analog Front End Data Sheet-1

Low Cost, Low Power CMOS General Purpose Analog Front End AD73311 FEATURES 16-Bit A/D Converter 16-Bit D/A Converter Programmable Input/Output Sample Rates 75 dB ADC SNR 70 dB DAC SNR 64 kS/s Maximum Sample Rate –90 dB Crosstalk Low Group Delay (25 ␮s Typ per ADC Channel, 50 ␮s Typ per DAC Channel) Programmable Input/Output Gain Flexible Serial Port which Allows up to 8 Devices to Be Connected in Cascade Single (+2.7 V to +5.5 V) Supply Operation 50 mW Max Power Consumption at 2.7 V On-Chip Reference 20-Lead SOIC/SSOP Package GENERAL DESCRIPTION The AD73311 is a complete front-end processor for general purpose applications including speech and telephony. It features a 16-bit A/D conversion channel and a 16-bit D/A conversion channel. Each channel provides 70 dB signal-to-noise ratio over a voiceband signal bandwidth. The final channel bandwidth can be reduced, and signal-to-noise ratio improved, by external digital filtering in a DSP engine. The AD73311 is suitable for a variety of applications in the speech and telephony area including low bit rate, high quality compression, speech enhancement, recognition and synthesis. The low group delay characteristic of the part makes it suitable for single or multichannel active control applications. The gains of the A/D and D/A conversion channels are programmable over 38 dB and 21 dB ranges respectively. An on-chip reference voltage is included to allow single supply operation. A serial port (SPORT) allows easy interfacing of single or cascaded devices to industry standard DSP engines. APPLICATIONS General Purpose Analog I/O Speech Processing Cordless and Personal Communications Telephony Active Control of Sound & Vibration Data Communications The AD73311 is available in both 20-lead SOIC and SSOP packages. FUNCTIONAL BLOCK DIAGRAM AVDD1 ANALOG SIGMA-DELTA MODULATOR DECIMATOR SCLK VINN SERIAL I/O PORT VOUTP +6/–15dB PGA VOUTN REFCAP CONTINUOUS TIME LOW-PASS FILTER SWITCHEDCAPACITOR LOW-PASS FILTER DIGITAL SIGMA-DELTA MODULATOR SDO SDOFS SE MCLK RESET REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000

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AD73311: Low Cost, Low Power CMOS General Purpose Analog Front End Data Sheet-2

+3 DVDD +3 V 10%; DGND = AGND AD73311–SPECIFICATIONS1 (AVDD64=kHz;VT؎=10%; to T =, unless؎otherwise noted) = 0 V, f F = T Parameter REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, VREFOUT Minimum Load Resistance Maximum Load Capacitance Total Harmonic Distortion PGA = 0 dB PGA = 38 dB Intermodulation Distortion Idle Channel Noise Crosstalk DC Offset Power Supply Rejection Differential Nominal Voltage Output Swing (0 dBm0) Single-Ended Differential Total Harmonic Distortion PGA = 0 dB PGA = 6 dB Intermodulation Distortion Idle Channel Noise...

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AD73311: Low Cost, Low Power CMOS General Purpose Analog Front End Data Sheet-3

AD73311 Parameter DAC SPECIFICATIONS (Continued) Power Supply Rejection LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IIH, Input Current CIN, Input Capacitance Test Conditions/Comments Output DC Offset 2, 7 Minimum Load Resistance, R L2, 8 Single-Ended Differential Maximum Load Capacitance, CL2, 8 Single-Ended Differential FREQUENCY RESPONSE (ADC AND DAC)9 Typical Output 0 Hz 2000 Hz 4000 Hz 8000 Hz 12000 Hz 16000 Hz 20000 Hz 24000 Hz 28000 Hz > 32000 Hz Input Signal Level at AVDD and DVDD Pins: 1.0 kHz, 100 mV p-p Sine Wave 64 kHz Input Sample Rate, Interpolator Bypassed (CRE:5...

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AD73311: Low Cost, Low Power CMOS General Purpose Analog Front End Data Sheet-4

+5 +5 V 10%; DGND = AGND AD73311–SPECIFICATIONS1 (AVDD64=kHz;VT؎=10%; DVDD =, unless؎otherwise noted) = 0 V, f F = T to T Minimum Load Resistance Maximum Load Capacitance ADC SPECIFICATIONS Maximum Input Range at VIN2, 3 Test Conditions/Comments 5VEN = 0 5VEN = 1 0.1 µF Capacitor Required from REFCAP to AGND2 REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, V REFOUT REFERENCE REFCAP Absolute Voltage, V REFCAP 1.0 kHz, 0 dBm0 1.0 kHz, 0 dBm0 1.0 kHz, +3 dBm0 to –50 dBm0 Refer to Figure 5 300 Hz to 3.4 kHz Frequency Range 0 Hz to 32 kHz Frequency Range 300 Hz to 3.4 kHz Frequency Range...

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AD73311: Low Cost, Low Power CMOS General Purpose Analog Front End Data Sheet-5

Test Conditions/Comments Output DC Offset 2, 7 Minimum Load Resistance, R L2, 8 Single-Ended Differential Maximum Load Capacitance, CL2, 8 Single-Ended Differential Input Signal Level at AVDD and DVDD Pins: 1.0 kHz, 100 mV p-p Sine Wave 64 kHz Input Sample Rate, Interpolator Bypassed (CRE:5 = 1) PGA = 6 dB DAC SPECIFICATIONS (Continued) Power Supply Rejection FREQUENCY RESPONSE (ADC AND DAC)9 Typical Output 0 Hz 2000 Hz 4000 Hz 8000 Hz 12000 Hz 16000 Hz 20000 Hz 24000 Hz 28000 Hz > 32000 Hz LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IIH, Input Current CIN, Input Capacitance...

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AD73311: Low Cost, Low Power CMOS General Purpose Analog Front End Data Sheet-6

AD73311 Table II. Current Summary (AVDD = DVDD = +5.5 V) Internal Digital Current 6 6 0 External Interface Current 2 2 0 Conditions ADC On Only ADC and DAC On REFCAP On Only REFCAP and REFOUT On Only All Sections Off Comments REFOUT Disabled REFOUT Disabled REFOUT Disabled MCLK Active Levels Equal to 0 V and DVDD Digital Inputs Static and Equal to 0 V or DVDD The above values are in mA and are typical values unless otherwise noted. Table III. Signal Ranges Maximum Input Range at VIN Nominal Reference Level Maximum Voltage Output Swing Single-Ended Differential Nominal Voltage Output Swing Single-Ended...

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AD73311: Low Cost, Low Power CMOS General Purpose Analog Front End Data Sheet-7

AD73311 (AVDD = +5 V ؎ 10%; DVDD = +5 V ؎ 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted) TIMING CHARACTERISTICS Parameter See Figure 1 MCLK Period MCLK Width High MCLK Width Low See Figures 3 and 4 SCLK Period SCLK Width High SCLK Width Low SDI/SDIFS Setup Before SCLK Low SDI/SDIFS Hold After SCLK Low SDOFS Delay from SCLK High SDOFS Hold After SCLK High SDO Hold After SCLK High SDO Delay from SCLK High SCLK Delay from MCLK * SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE). Figure 3. SCLK Timing Figure 2. Load Circuit for Timing Specifications Figure 1....

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