AMD Athlon™ 64 X2 Dual-Core Processor Product Data Sheet • Compatible with Existing 32-Bit Code Base * Including support for SSE, SSE2, SSE3 , MMX™, 3DNow!™ technology and legacy x86 instructions *SSE3 supported by Rev E and later processors. Runs existing operating systems and drivers Local APIC on-chip AMD64 Technology – AMD64 technology instruction set extensions – 64-bit integer registers, 48-bit virtual addresses, 939-Pin Package Specific Features 40-bit physical addresses – Eight additional 64-bit integer registers (16 total) • Refer to the AMD Functional Data Sheet, – Eight additional 128-bit SSE/SSE2/SSE3 registers 939-Pin Package, order# 31411, for functional, (16 total) electrical, and mechanical details of 939-pin package processors. Dual-Core Architecture – Discrete L1 and L2 cache structures for each core • Electrical Interfaces – HyperTransport™ Technology to I/O Devices – One 16-bit link supporting speeds up to 1 GHz (2000 MT/s) or 4 Gigabytes/s in each direction 64-Kbyte 2-Way Associative ECC-Protected L1 Data Caches – Two 64-bit operations per cycle, 3-cycle latency 64-Kbyte 2-Way Associative Parity-Protected L1 Instruction Caches – With advanced branch prediction 16-Way Associative ECC-Protected L2 Caches – Exclusive cache architecture—storage in addition to L1 caches – Up to 1 Mbyte per L2 cache Power Management – Multiple low-power states including C1E* *C1E supported by Rev. G or later processors. – System Management Mode (SMM) – ACPI-compliant, including support for processor performance states Packaging – 939-pin lidded micro PGA – 1.27-mm pin pitch – 31x31-row pin array – 40mm x 40mm organic substrate – Organic C4 die attach Integrated Memory Controller – Low-latency, high-bandwidth – 144-bit DDR SDRAM at 100, 133, 166, and 200 MHz – Supports up to four unbuffered DIMMs – ECC checking with double-bit detect and single-bit correct Machine Check Architecture – Includes hardware scrubbing of major ECC-protected arrays Publication # Issue Date: HyperTransport™ technology: LVDS-like differential, unidirectional DDR SDRAM: SSTL_2 per JEDEC specification Clock, reset, and

AMD Athlon™ 64 X2 Dual Core Product Data Sheet Socket AM2 Specific Features • Refer to the Socket AM2 Processor Functional Data Sheet, order# 31117, for functional and mechanical details of socket AM2 processors. Refer to the AMD NPT 0Fh Family Processor Electrical Data Sheet, order# 31119, for electrical details of socket AM2 processors. Electrical Interfaces – HyperTransport™ technology: LVDS-like differential, unidirectional – DDR2 SDRAM: SSTL_1.8 per JEDEC specification – Clock, reset, and test signals also use DDR2 SDRAM-like electrical specifications Packaging – Lidded micro PGA – 31x31...

AMD Athlon™ 64 X2 Dual Core Product Data Sheet Revision History Date Fourth Public release. Added support for the C1E low-power state in Rev. G or later processors. Third Public release. Added RoHS compliance statement. Added asterisk note to SSE3. Public release. • Added Socket AM2 Specific Features • Created heading for 939-Pin Package Specific Features • Placed Electrical Interfaces, Packaging, and Integrated Memory Controller bullets under the new 939-Pin Package Specific Features heading. Initial public release. © 2005 – 2007 Advanced Micro Devices, Inc. All rights reserved. The contents...