GC-IP200
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GC-IP200 Datasheet Version: 2.2 Date: 31/01/2017 AMAC ASIC- und Mikrosensoranwendung Chemnitz GmbH Kopernikusstr. 16 D-09117 Chemnitz Germany

Revision History Date First preparation Diverse modifications and additions SPI protocol corrections, supplementation of mechanical and electrical parameters change to new AMAC document layout © Copyright 2017 AMAC ASIC- und Mikrosensoranwendung Chemnitz GmbH Subject to change without prior notice. Our policy is one of continuous improvement, and consequently the equipment may vary slightly from the description and specifications in this publication. The specifications, illustrations and descriptions provided in this documentation are not binding in detail. No part of this publication may...

1 Overview The GC-IP200 interpolation circuit is designed for connection to incremental position and angle measuring systems with sine-shaped output signals with a 90° phase shift. It can be operated at a large number of transducer systems working according to the most varied measuring principles. With a maximum interpolation rate of 200 the IC is capable to split the input signal period into up to 200 segments. A counter value can be output via parallel or serial interface, respectively. Different interfaces and flexible configuration types enable the use of the GC-IP200 in single-chip...

Input Signals 3 Input Signals The two input signals for the interpolation function are analogue voltages (sine/cosine) with a sine-shaped dependency on the measured value (position or angle respectively) with a phase shift of 90° between these two analogue voltages, related to one period of the scale. A third input signal serves as a reference signal for determining the zero or reference point of the scale. All the three input signals are processed as differential signals. 3.1 Analogue Signal Properties Difference Signal Sin = SinP-SinN Angle 0° Vdiff Peak to Peak SinP SinN 90° Phase Shift...

Input Signals 3.3 Reference Signals / Index Point A third output of the measuring system - typically called reference, index point or zero point signal considered to be activated, if the difference of the signals at the REFP and REFN pins becomes greater than the positive hysteresis voltage VRPH and is considered to be deactivated if this voltage becomes smaller than the negative hysteresis voltage VRPL. REFN REFP respectively: VRPH VRPL VRPL (typical) Hysteresis (typical) VRPH (typical) Figure 3: Reference Signals If a sensor without reference signals is used, defined levels on pins REFP...

Digital Operation Modes 5 Digital Operation Modes 5.1 Output Signals / Counter Value The position/angle result is available via the integrated serial interface in a 28-bit two's-complement format. As described, the zero point can be generated using the REFP and REFN reference signal inputs, or it can be set via the serial interface. By activating the trigger input, measuring result can be kept in a 2-level deep buffer register in a manner asynchronous to the access via the interfaces. Simultaneously, the GC-IP200 outputs the phase shifted square wave sequences (known by incremental...

Digital Operation Modes 5.4 Interval Time / Maximum Input Frequency The interval time (IT) and the minimum edge distance tpp at the output signals, respectively, can be set in binary steps at values between 1/fosz and 128/fosz. In counter mode (the SPEED Bit in the CFG0 Register being set), the maximum input frequency totals fmax=fosc /96. In all the other modes, the maximum input frequency is limited by the minimum pulse distance at the output, where: fmax  0.9*fOSZ /(IRIT) < fosz/96 fosc: Clock frequency at Pin XA IR: Activated Interpolation Rate IT: Activated Interval Time The limit...

6 Interfaces The measurement results can be read out over the integrated serial interface (SPI). It is also possible to make a more detailed configuration of the GC-IP200 IC over this interface than over hardware. For high speed applications the additional 16-bit wide parallel port allow to read out the measurement results continuously with up to 32MBit/s. 6.1 Structure WR-Register Bank Cycle Counter C-CNT Figure 6: interface structure 6.2 Serial Interface (SPI) The serial interface contains a 16-bit shift register for read accesses and write accesses each. An additional 16-bit hold...

Start command processing SCLK tVDI tSETDI tRDY Figure 7: SPI timing Table 4: SPI timing Name SPI clock, H time SPI clock, L time Waiting time between SEN falling and SCLK rising 4 x TOSZ + 15 ns Switching delay RDY / SDO from SEN Time between SCLK rising and data read Setup time SDI before SCLK 5 TOSZ + 15 ns Time between SCLK rising and data output 6.2.2 Protocol Table 5: SPI timing Bit No. at signal SDI 15 Write Address Write Data Write Command Output Read-Register command load the internal data into a 32-bit hold register 2) bit must be set to zero in single-channel systems Bit Broadcast...

6.2.3 Synchronous / Asynchronous Mode Read data is loaded into the hold register by the RD0/ST command. This takes place when the internal sequential control counter and the SYNC register have the same contents (synchronous mode) or when the ASYNC bit is set (asynchronous mode). Pin SDO is low during the waiting time (meaning of RDY) . With the SPI working in synchronous mode, the output data can be assigned to a sample time. Equidistant measurement is possible (refer also to the application example). Higher transmission rates are achieved in asynchronous mode. Example: 32-bit read access...

6.3 Parallel Data Port This interface outputs the last activated SPI read register synchronized to the GC-IP200 internal sequential control counter. The appearing data are separated into two 16-bit words. After reset, the data of the SPI read register address 0x00(MVAL)appears on DATA(15:0) by default. Sequential Control Counter OUTHIGH STRB XA Signal TDelay TDelay < 15ns Figure 12: timing Parallel Data Port To reduce switching noise on the data port the Data outputs DATA(15:8) will be switched 1 clock cycle after the outputs DATA(7:0). That's why the value at DATA(15:8) is undefined in the...