Agilent J-BERT N4903B High-Performance Serial BERT 7 Gb/s and 12.5 Gb/s Data Sheet Version 1.4 (USB 3.1 SKP OS ltering) Integrated Calibrated Automated Compliant Complete jitter tolerance test for embedded and forwarded clock devices

Agilent Technologies N4900 Series Agilent offers a wide range of serial bit error ratio test (BERT) solutions for R&D and manufacturing. The J-BERT N4903B highperformance serial BERT is the flagship of Agilent’s N4900 serial BERT series. It addresses the needs of R&D and validation teams who characterize serial I/O ports or ASICs up to 14.2 Gb/s. The data rate can be extended up to 28.4 Gb/s by adding a 2:1 multiplexer and demultiplexer with clock data recovery. Integrated and calibrated jitter sources for jitter tolerance measurements allow designers to characterize and prove compliance of their...

Serial BERTs for R&D and validation labs Serial BERTs for manufacturing test of optical transceivers The J-BERT M8020A is the new generation high-performance BERT that enables fast and accurate receiver characterization of single- and multi-lane devices operating up to 16 or 32 Gb/s. The N5980A manufacturing serial BERT up to 3.125 Gb/s data rate enables transceiver test at up to one-sixth of the test cost and the front panel size of comparable BERT solutions. The J-BERT N4903B high-performance serial BERT is the ideal choice for characterization. It offers calibrated jitter tolerance tests fully...

J-BERT N4903B High-Performance Serial BERT The J-BERT N4903B high-performance serial BERT provides the most complete jitter tolerance test for embedded and forwarded clock devices. signals from the pattern generator, which features exceptionally low jitter and extremely fast transition times. Built-in and calibrated jitter sources allow accurate jitter tolerance testing of receivers. It is the ideal choice for R&D and validation teams characterizing and stressing chips and transceiver modules that have serial I/O ports up to 7 Gb/s, 12.5 Gb/s or even 14.2 Gb/s. It can characterize a receiver’s...

J-BERT N4903B The Most Complete Jitter Tolerance Test Solution ance tests and fast total jitter measurements. The J-BERT N4903B is a long-term investment which is configu- rable for today's test and budget requirements but also allows upgrades from the N4903A model, and later retrofit of all options and full speed when test needs change. To expand the use of J-BERT a 4-tap de-emphasis, a reference clock multiplier, a 28 Gb/s 2:1 multiplexer, and a 32 Gb/s CDR with de-multiplexer can be added to the setup. Press Auto Align to automatically adjust the analyzer's sampling point delay and Pattern...

Jitter Tolerance Tests Calibrated and integrated jitter injection Periodic jitter, single and dual-tone (Option J10) Sinusoidal jitter (Option J10) Random jitter and spectrally distributed RJ (Option J10) Bounded uncorrelated jitter (Option J10) Intersymbol interference (ISI) (Option J20) Sinusoidal interference (Option J20) Spread spectrum clocking (SSC) and residual SSC (Option J11) External jitter injection Using an external source connected to delay control input. User controls Manual jitter composition This screen allows the user to set up combinations of jitter types and jitter magnitudes...

User Interface and Measurement Suite Quick eye diagram and masking The quick eye diagram allows a one-shot check for a valid signal. Due to the higher sampling depth of a BERT, the eye contour lines visualize the measured eye at a deeper BER level for more accurate results. Extrapolated eye contour lines display the eye opening for even lower BER levels, such as 1015, reducing the measurement time significantly. The display shows numerical results for 1- and 0- level, eye amplitude and width, total jitter and more. Eye masks can be loaded from a library. Violations of the captured eye mask are...

User Interface Bit recovery mode (Option A01) This mode is useful for analyzing non-deterministic traffic. This is helpful when you need to analyze real world traffic, for example in a PCI Express link, where so-called 'skip ordered sets' are added unpredictably to avoid FIFO overflow. This simplifies setup by eliminating the need to setup expected data for the error detector. Two analyzer sampling points are used to measure a relative BER, which makes the following measurements possible with relative BERT scan including RJ/DJ separation Output levels and Q factor Fast total jitter Spectral jitter...

Specifications-Pattern Generator Pattern generator key characteristics: • Available as 7 and 12.5 Gb/s pattern generator without error detector (Options G07 and G13), extension to Differential outputs with variable output levels for data, aux data, clock and trigger Half-rate clock with variable duty cycle (Option 003) Pattern sequencer with up to 120 blocks and counted Second output channel (Option 002) Calibrated and integrated jitter injection with SJ, two- tone PJ, RJ/sRJ, BUJ, ISI, S.I. (Option J10, J20) Automated jitter tolerance characterization sweep makes use of SJ and PJ using 610 ps...

Speciications-Pattern Generator Data output and auxiliary data output (DATA OUT, AUX DATA OUT) Table 2. Output characteristics for J-BERT N4903B generator. All timing parameters are measured at ECL levels. 150 Mb/s to 14.2 Gb/s (Option D14, required in addition to C13 or G13) 150 Mb/s to 12.5 Gb/s (Option C13 or G13); can be programmed up to 13.5 Gb/s 150 Mb/s to 7 Gb/s (Option C07 or G07); < 620 MHz only with external clock Frequency accuracy Electrical idle Output transitions from full swing signal to 0 V amplitude and vice versa at constant offset within 4 ns typ. Electrical idle is controlled...

Pattern Generator Speciications Clock output (CLK OUT) 1/z Clock can operate at full bit-rate or at half bit-rate (Option 003) to support testing of forward clocked devices. Table 3. Clock output specications Internal clock Frequency range 150 MHz to 14.2 GHz (Option D14, in addition to C13 or G13); 150 MHz to 12.5 GHz (Option C13 or G13); can be programmed up to 13.5 GHz 150 MHz to 7 GHz (Option C07 or G07); < 620 MHz only with external clock Half-rate clocking Output voltage window External termination voltage < -75 dBc with internal clock source, 10 GHz at 10 kHz offset, 1 Hz bandwidth Table...