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LTC 6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution

LTC 6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution
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LTC 6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution - 1

LTC6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution Description Features Low Phase Noise and Jitter n Additive Jitter: 18fs RMS (12kHz to 20MHz) n Additive Jitter: 85fs RMS (10Hz to Nyquist) n EZSync™ Multichip Clock Edge Synchronization n Full PLL Core with Lock Indicator n –226dBc/Hz Normalized In-Band Phase Noise Floor n –274dBc/Hz Normalized 1/f Phase Noise n 1.4GHz Maximum VCO Input Frequency n Four Independent, Low Noise 1.4GHz LVPECL Outputs n One LVDS/CMOS Configurable Output n Five Independently Programmable Dividers Covering All Integers from 1 to 63 n Five Independently Programmable VCO Clock Cycle Delays Covering All Integers from 0 to 63 n –40°C to 105°C Junction Temperature Range n Applications Clocking High Speed, High Resolution ADCs, DACs and Data Acquisition Systems n Low Jitter Clock Generation and Distribution n The LTC®6950 is a low phase noise integer-N frequency synthesizer core with clock distribution. The LTC6950 delivers the low phase noise clock signals demanded in high frequency, high resolution data acquisition systems. The frequency synthesizer contains a full low noise PLL core with a programmable reference divider (R), a programmable feedback divider (N), a phase/frequency detector (PFD) and a low noise charge pump (CP). The clock distribution section of the LTC6950 delivers up to five outputs based on the VCO input. Each output is individually programmed to divide the VCO input frequency by any integer from 1 to 63 and to delay the output by 0 to 63 VCO clock cycles. Four of the outputs feature very low noise, low skew LVPECL logic signals capable of operation up to 1.4GHz. The fifth output is selectable as either an LVDS (800MHz) or CMOS (250MHz) logic type. This output is also programmed to produce an output signal based on either the VCO input or the reference divider output. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and EZSync and ClockWizard are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 8,319,551 and 8,819,472. VCP+ PHASE FREQUENCY DETECTOR CHARGE PUMP SYNC CONTROL SERIAL PORT DIVIDE 1 TO 63 DIVIDE 1 TO 63 DIVIDE 1 TO 63 PECLx Closed-Loop Phase Noise, fVCSO = 1GHz, Mx[5:0] = 8, fPECLx = 125MHz ABSOLUTE PHASE NOISE (dBc/Hz)

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LTC 6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution - 2

LTC6950 Absolute Maximum Ratings UHH PACKAGE 48-LEAD (5mm × 9mm) PLASTIC QFN TJMAX = 150°C, θJCbottom = 2°C/W, θJCtop = 12°C/W EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH PART MARKING PACKAGE DESCRIPTION JUNCTION TEMPERATURE RANGE Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to:...

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LTC 6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution - 3

The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). V+ = VREF+ = VVCO+ = VP0+ = VP1+ = VP2+ = VP3+ = 3.3V, VCP+ = 5V unless otherwise specified. All voltages are with respect to ground. SYMBOL Reference Inputs (REF+, REF–) fREF VREF Input Frequency Input Signal Level Minimum Input Slew Rate DCREF Input Duty Cycle Self-Bias Voltage Maximum Common Mode Level Minimum Input Signal Detected NO_REF = 0, 2MHz ≤ fREF ≤ 250MHz, Sine Wave Maximum Input Signal Not Detected NO_REF = 1, 2MHz ≤ fREF ≤ 250MHz,...

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LTC 6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution - 4

The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). V+ = VREF+ = VVCO+ = VP0+ = VP1+ = VP2+ = VP3+ = 3.3V, VCP+ = 5V unless otherwise specified. All voltages are with respect to ground. SYMBOL Output Source/Sink Current Range Output Source/Sink Current Accuracy Output Hi-Z Leakage Current ICP = 350µA, CPCLO = CPCHI = 0 (Note 3) ICP = 700µA, CPCLO = CPCHI = 0 (Note 3) ICP = 11.2mA, CPCLO = CPCHI = 0 (Note 3) Output Source/Sink Current Matching Output Source/Sink Current vs Output Voltage...

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LTC 6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution - 5

The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). V+ = VREF+ = VVCO+ = VP0+ = VP1+ = VP2+ = VP3+ = 3.3V, VCP+ = 5V unless otherwise specified. All voltages are with respect to ground. SYMBOL Divider Delay in VCO Clock Cycles DEL0[5:0], DEL1[5:0], DEL2[5:0], DEL3[5:0], DEL4[5:0] Single-Ended Termination = 50Ω to (VPx+ – 2V) Single-Ended Termination = 50Ω to (VPx+ – 2V) Single-Ended Termination = 50Ω to (VPx+ – 2V) Common Mode Voltage (Outputs Static) Differential Voltage (Outputs Static)...

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LTC 6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution - 6

The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). V+ = VREF+ = VVCO+ = VP0+ = VP1+ = VP2+ = VP3+ = 3.3V, VCP+ = 5V unless otherwise specified. All voltages are with respect to ground. SYMBOL LVDS Clock Outputs (LV/CM+ and LV/CM–) fLVDS Differential Voltage (Outputs Static) Offset Voltage (Outputs Static) |ISA|, |ISB| Short Circuit Current to Common Short Circuit Current to Complementary Duty Cycle RDIVOUT = 0, M4[5:0] = 1 RDIVOUT = 1, R[9:0] = 1, M4[5:0] = 1 RDIVOUT = 0, M4[5:0] > 1 (Even or...

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LTC 6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution - 7

The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). V+ = VREF+ = VVCO+ = VP0+ = VP1+ = VP2+ = VP3+ = 3.3V, VCP+ = 5V unless otherwise specified. All voltages are with respect to ground. SYMBOL CMOS Clock Outputs (LV/CM+ and LV/CM–) fCMOS High Voltage (Outputs Static) Low Voltage (Outputs Static) Duty Cycle RDIVOUT = 0, M4[5:0] = 1 RDIVOUT = 1, R[9:0] = 1, M4[5:0] = 1 RDIVOUT = 0, M4[5:0] > 1 (Even or Odd) RDIVOUT = 1, M4[5:0] > 1 (Even) RDIVOUT = 1, R[9:0] = 3, M4[5:0] = 3 RDIVOUT = 1, R[9:0] =...

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