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ADL9006

ADL9006
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2 GHz to 28 GHz, GaAs, pHEMT, MMIC, Low Noise Amplifier ADL9006CHIPS Data Sheet FEATURES GENERAL DESCRIPTION P1dB: 19 dBm typical at 2 GHz to 14 GHz at 2 GHz to 14 GHzGain: 15.5 dB typical at 14 GHz to 22 GHz Noise figure: 2.2 dB at 2 GHz to 14 GHz Output IP3: 24 dBm typical at 2 GHz to 14 GHz Power supply voltage: 5 V with a 55 mA total supply current 50 Ω matched input and output The ADL9006CHIPS is a gallium arsenide (GaAs), pseudomorphic high electron mobility transistor (pHEMT), monolithic microwave integrated circuit (MMIC), low noise amplifier that operates from 2 GHz to 28 GHz. The amplifier provides 15.5 dB of gain, 2.2 dB of noise figure, 24 dBm of output third-order intercept (IP3), 20 dBm of output saturated power (PSAT), and 19 dB of power output for 1 dB compression (P1dB) while requiring a 55 mA power supply current (IDD) from a 5 V total supply voltage. The ADL9006CHIPS is self biased with only a single positive supply needed to achieve an IDD of 55 mA. APPLICATIONS Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military and space The ADL9006CHIPS amplifier input and output are internally matched to 50 Ω facilitating integration into multichip modules (MCMs). FUNCTIONAL BLOCK DIAGRAM 5 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2021 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

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Data Sheet REVISION HISTORY 1/2021—Revision 0: Initial Versi

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Data Sheet SPECIFICATIONS 2 GHz TO 14 GHz VDD = 5 V, IDD = 55 mA, VGG2 = open, and TA = 25°C, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE GAIN Gain Variation over Temperature RETURN LOSS Input Output OUTPUT Power for 1 dB Compression Saturated Power Third-Order Intercept Second-Order Intercept NOISE FIGURE Test Conditions/Comments 18 Measurement taken at output power (POUT) per tone = 0 dBm Measurement taken at POUT per tone = 0 dBm 14 GHz TO 22 GHz VDD = 5 V, IDD = 55 mA, VGG2 = open, and TA = 25°C, unless otherwise noted. Table 2. Parameter FREQUENCY RANGE GAIN Gain...

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Data Sheet 22 GHz TO 28 GHz VDD = 5 V, IDD = 55 mA, VGG2 = open, and TA = 25°C, unless otherwise noted. Table 3. Parameter FREQUENCY RANGE GAIN Gain Variation over Temperature RETURN LOSS Input Output OUTPUT Saturated Power Third-Order Intercept Second-Order Intercept NOISE FIGURE Test Conditions/Comments 15 Measurement taken at POUT per tone = 0 dBm Measurement taken at POUT per tone = 0 dBm DC SPECIFICATIONS Table 4. Parameter TOTAL SUPPLY CURRENT POWER SUPPLY VOLTAGE VGG2 Test Conditions/Comments VDD = 5 V VGG2 = open (nominal condition)

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Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter Drain Bias Voltage Gate Control (VGG2) RFIN Continuous Power Dissipation (PDISS) at TDIE BOTTOM = 85°C (Derate 22.1 mW/°C above 85°C) Temperature Storage Range Operating Range (Die Bottom) Channel to Maintain 1,000,000 Hour Meant Time to Failure (MTTF) Nominal Channel (TA = 85°C, VDD = 5 V) Thermal performance is directly linked to system design and operating environment. Careful attention to printed circuit board (PCB) thermal design is required. θJC is the channel to case, thermal resistance, channel to bottom of...

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Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 5 TOP VIEW (CIRCUIT SIDE) NOTES 1. NC = NO CONNECT. SEE THE ASSEMBLY DIAGRAM, FIGURE 42, FOR PROPER BONDING. Table 8. Pad Function Descriptions Pad No. 1, 3, 6, 8, 9 Description Ground. The GND pads are connected to the die bottom using thru die vias. See the assembly diagram for proper bonding (see Figure 42). See Figure 5 for the interface schematic. RF Input. RFIN is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic. Gain Control. VGG2 is dc-coupled and accomplishes gain control by reducing the internal voltage...

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Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS SMALL SIGNAL RESPONSE 20 Figure 8. Gain and Return Loss vs. Frequency Figure 11. Gain vs. Frequency at Various Temperatures Figure 12. Gain vs. Frequency at Various VGG2 Voltages Figure 9. Gain vs. Frequency at Various Supply Voltages 0 Figure 13. Reverse Isolation vs. Frequency at Various Temperatures Figure 10. Gain vs. VGG2 for Various Frequencies

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Data Sheet Figure 17. Output Return Loss vs. Frequency at Various Temperatures 0 4V 5V 6V 7V OUTPUT RETURN LOSS (dB) Figure 15. Input Return Loss vs. Frequency at Various Supply Voltages Figure 18. Output Return Loss vs. Frequency at Various Supply Voltages –5 OUTPUT RETURN LOSS (dB) Figure 16. Input Return Loss vs. Frequency at Various VGG2 Voltages INPUT RETURN LOSS (dB) Figure 14. Input Return Loss vs. Frequency at Various Temperatures INPUT RETURN LOSS (dB) OUTPUT RETURN LOSS (dB) INPUT RETURN LOSS (dB)

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Data Sheet Figure 20. Noise Figure vs. Frequency at Various Supply Voltages Figure 21. Noise Figure vs. Frequency at Various Temperatures

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Data Sheet LARGE SIGNAL RESPONSE 26 Figure 22. PSAT vs. Frequency at Various Temperatures Figure 25. PSAT vs Frequency at Various VGG2 Voltages Figure 26. POUT vs. Frequency at Various Input Power Levels Figure 23. PSAT vs. Frequency at Various Supply Voltages 25 Figure 24. POUT, Gain, Power Added Efficiency (PAE), and IDQ vs. Input Power, 2 GHz, VDD = 5 V Figure 27. POUT, Gain, PAE, and IDQ vs. Input Power, 10 GHz, VDD = 5 V

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Data Sheet Figure 31. POUT, Gain, PAE, and IDQ vs. Input Power, 26 GHz, VDD = 5 V 30 Figure 32. Output IP3 vs. Frequency at Various Supply Voltages at POUT = 0 dBm per Tone Figure 29. Output IP3 vs. Frequency for Various Temperatures at POUT = 0 dBm per Tone Figure 30. Output IP3 vs. Frequency at Various VGG2 Voltages Figure 33. Output IP3 vs. VGG2 for Various Frequencies Figure 28. POUT, Gain, PAE, and IDQ vs. Input Power, 20 GHz, VDD = 5 V

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