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AD4115

AD4115
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Data Sheet Single-Supply, Multichannel, 125 kSPS, 24-Bit, Sigma-Delta ADC with ±10 V Inputs AD4115 GENERAL DESCRIPTION 24-bit ADC with integrated AFE Fast and flexible output rate: 2.5 SPS to 125 kSPS Channel scan data rate of 24,845 SPS per channel (40.25 µs settling) 85 dB common mode rejection of 50 Hz and 60 Hz at 20 SPS per channel ±10 V inputs, either 8 differential or 16 single-ended VIN pin absolute maximum rating ±65 V Absolute input pin voltage up to ±20 V Minimum 1 MΩ impedance On-chip 2.5 V reference ±0.12% initial accuracy at 25°C, ±5 ppm/°C (typical) drift Internal or external clock Power supplies AVDD = 4.5 V to 5.5 V IOVDD = 2 V to 5.5 V Total current consumption AVDD + IOVDD (IDD) = 10.4 mA Temperature range: −40°C to +105°C 3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK) SPI, QSPI, MICROWIRE, and DSP compatible The AD4115 is a low power, low noise, 24-bit, sigma-delta (Σ-Δ) analog-to-digital converter (ADC) that integrates an analog front end (AFE) for eight fully differential or 16 single-ended, high impedance (≥1 MΩ), bipolar, ±10 V voltage inputs. APPLICATIONS Process control Programmable logic controller (PLC) and distributed control system (DCS) modules Instrumentation and measurement The AD4115 integrates key analog and digital signal conditioning blocks to configure eight individual setups for each analog input channel in use. The AD4115 features a maximum channel scan rate of 24,845 kSPS (40.25 µs) for fully settled data. The embedded 2.5 V, low drift (±5 ppm/°C), band gap internal reference (with output reference buffer) reduces the external component count. The digital filter allows flexible settings, including simultaneous 50 Hz and 60 Hz rejection at a 27.27 SPS output data rate. The user can select different filter settings depending on the requirements of each channel in the application. The automatic channel sequencer enables the ADC to switch through each enabled channel. The precision performance of the AD4115 is achieved by integrating the proprietary iPassives® technology from Analog Devices, Inc. The AD4115 is factory calibrated to achieve a high degree of specified accuracy. The AD4115 operates with a single power supply that allows simplified use in galvanically isolated applications. The specified operating temperature range is −40°C to +105°C. The AD4115 is housed in a 40-lead, 6 mm × 6 mm LFCSP. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Techn

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Data Sheet

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Data Sheet

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Data Sheet FUNCTIONAL BLOCK DIAGRAM AVDD BUFFERED PRECISION REFERENCE INTERNAL REFERENCE RAIL-TO-RAIL REFERENCE INPUT BUFFERS PRECISION VOLTAGE DIVIDER CS SCLK DIGITAL FILTER SERIAL INTERFACE DIN DOUT/RDY SYNC ERROR XTAL AND INTERNAL CLOCK OSCILLATOR CIRCUITRY

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Data Sheet SPECIFICATIONS AVDD = 4.5 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = 0 V, DGND = 0 V, VBIAS− = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock (MCLK) = 8 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted. VREF is the reference voltage, FS is full scale, and FSR is full-scale range. Table 1. Parameter VOLTAGE INPUTS Differential Input Voltage Range1 Absolute Input Pin Voltage Input Impedance Offset Error 2 Offset Drift Gain Error Gain Drift Integral Nonlinearity (INL) Total Unadjusted Error (TUE) 3 Power Supply Rejection Ratio (PSRR) Common-Mode Rejection Ratio...

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AD4115 Parameter Buffers Disabled Input Current Input Current Drift Buffers Enabled Input Current Input Current Drift Normal Mode Rejection CMRR TEMPERATURE SENSOR Accuracy Sensitivity GENERAL-PURPOSE OUTPUTS (GPIO0, GPIO1, GPO2, GPO3) Floating State Output Capacitance Output Voltage3 High (VOH) Low (VOL) CLOCK Internal Clock Frequency Accuracy Duty Cycle Output Voltage VOH VOL Crystal Frequency Start-Up Time External Clock (CLKIO) Duty Cycle LOGIC INPUTS Input Voltage3 High (VINH) Low (VINL) Hysteresis Leakage Current LOGIC OUTPUT (DOUT/RDY) Output Voltage3 VOH Leakage Current3 Output...

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Data Sheet Parameter AVDD to AVSS AVSS to DGND IOVDD to DGND IOVDD to AVSS POWER SUPPLY CURRENTS 6 Full Operating Mode AVDD Current IOVDD Current Standby Mode Power-Down Mode POWER DISSIPATION Full Operating Mode Standby Mode Power-Down Mode Test Conditions/Comments For AVSS < DGND All outputs unloaded, digital inputs connected to IOVDD or DGND Including internal reference Internal clock All VIN = 0 V All VIN = 0 V The full specification is guaranteed for a differential input signal of ±10 V. The device is functional up to a differential input signal of ±VREF × 10. However, the specified...

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Data Sheet Figure 2. Read Cycle Timing Diagram Figure 3. Write Cycle Timing Diagram

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Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Parameter AVDD to AVSS AVDD to DGND IOVDD to DGND IOVDD to AVSS AVSS to DGND VINx to AVSS Reference Input Voltage to AVSS Digital Input Voltage to DGND Digital Output Voltage to DGND Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Soldering, Reflow Temperature Rating −0.3 V to +6.5 V...

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