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AD4114

AD4114
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24-bit ADC with integrated AFE Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS per channel (161 ms settling) 17.3 noise free bits at 1007 SPS per channel 120 dB common mode rejection of 50 Hz and 60 Hz at 20 SPS per channel ±10 V inputs, either 8 differential or 16 single-ended VIN pin absolute maximum rating: ±65 V Absolute input pin voltage up to ±20 V Minimum 1 Mft impedance 0.07% TUE at 25°C On-chip 2.5 V reference ±0.12% initial accuracy at 25°C, ±5 ppm/°C (typical) drift Internal or external clock Power supplies AVDD = 3.0 V to 5.5 V IOVDD = 2 V to 5.5 V Total current consumption AVDD + IOVDD (Idd) = 3.9 mA Temperature range: -40°C to +105°C 3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK) SPI, QSPI, MICROWIRE, and DSP compatible APPLICATIONS Process control Programmable logic controller (PLC) and distributed control system (DCS) modules Instrumentation and measurement The AD4114 is a low power, low noise, 24-bit, sigma-delta (Z-A) analog-to-digital converter (ADC) that integrates an analog front end (AFE) for fully differential or single-ended, high impedance (>1 MO), bipolar, ±10 V voltage inputs. The AD4114 integrates key analog and digital signal conditioning blocks to configure eight individual setups for each analog input channel in use. The AD4114 features a maximum channel scan rate of 6.21 kSPS (161 ps) for fully settled data. The embedded 2.5 V, low drift (±5 ppm/°C), band gap internal reference (with output reference buffer) reduces the external component count. The digital filter allows flexible settings, including simultaneous 50 Hz and 60 Hz rejection at a 27.27 SPS output data rate. The user can select different filter settings depending on the requirements of each channel in the application. The automatic channel sequencer enables the ADC to switch through each enabled channel. The precision performance of the AD4114 is achieved by integrating the proprietary (Passives* technology from Analog Devices, Inc. The AD4114 is factory calibrated to achieve a high degree of specified accuracy. The AD4114 operates with a single power supply that allows simplified use in galvanically isolated applications. The specified operating temperature range is -40°C to +105°C. The AD4114 is housed in a 40-lead, 6 mm x 6 mm LFCSP. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

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Data Sheet

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Data Sheet FUNCTIONAL BLOCK DIAGRAM AVDD BUFFERED PRECISION REFERENCE INTERNAL REFERENCE RAIL-TO-RAIL REFERENCE INPUT BUFFERS PRECISION VOLTAGE DIVIDER DIGITAL FILTER SERIAL INTERFACE DIN DOUT/RDY SYNC ERROR GPO CONTROL TEMPERATURE SENSOR XTAL AND INTERNAL CLOCK OSCILLATOR CIRCUITRY

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Data Sheet SPECIFICATIONS AVDD = 3.0 V to 5.5 V, IOVDD = 2 V (MCLK) = 2 MHz, Ta = Tmin to Tmax (full-scale range. Table 1. to 5.5 V, REF- = AVSS = 0 V, DGND = 0 V, VBIAS- = 0 V, REF+ = 2 -40°C to +105°C), unless otherwise noted. Vref is the reference voltage, 5 V, internal master clock FS is full scale, and FSR is Test Conditions/Comments VOLTAGE INPUTS Differential Input Voltage Range1 Absolute Input Pin Voltage Input Impedance Offset Error2 Offset Drift Gain Error Gain Drift Integral Nonlinearity (INL) Total Unadjusted Error (TUE)3 Power Supply Rejection Ratio (PSRR) Common-Mode Rejection...

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1 Sample tested during initial release to ensure compliance. 2 See Figure 2 and Figure 3. 3 This parameter is defined as the time required for the output to cross the Vol or Voh limit. 4 The SCLK active edge is the falling edge of SCLK. _ 5 DOUT/RDY returns high after a data register read. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while DOUT/RDY is high. Ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. Figure 3. Write...

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Data SheetABSOLUTE MAXIMUM RATINGS Ta = 25°C, unless otherwise noted. ESD CAUT ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

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AD4114 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS uuuuuuuuuu VINCOM VINO VIN1 VIN2 VIN3 REFOUT REGCAPA AVSS AVDD DNC S NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT ANYTHING TO DNC. DNC IS INTERNALLY CONNECTED TO AVSS. 2. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A SIMILAR PAD ON THE PCB THAT IS UNDER THE EXPOSED PAD TO CONFER MECHANICAL STRENGTH TO THE PACKAGE AND FOR HEAT DISSIPATION. THE EXPOSED PAD MUST BE CONNECTED TO AVSS THROUGH THIS PAD ON THE PCB. Figure 4. Pin Configuration Table 6. Pin Function Descriptions Mnemonic VINCOM VINO VIN1 VIN2 VIN3 REFOUT REGCAPA 2 Description Voltage...

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Data Sheet Pin No. Mnemonic 1 Type 18 ERROR 2 Description operate in 3-wire mode with SCLK, DIN, and DOUT/RDY used to interface with the device. When CS is high, the DOUT/RDY output is tristated. Error Input/Output or General-Purpose Output. ERROR can be used in one of the following three modes: Active low error input mode. This mode sets the ADC_ERROR bit in the status register. Active low, open-drain error output mode. The status register error bits are mapped to the ERROR pin. The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any...

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