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Samsung S6B0108 LCD Driver

Samsung S6B0108 LCD Driver
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64 CH SEGMENT DRIVER FOR DOT MATRIX LCD Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD INTRODUCTION The S6B0108 is a LCD driver LSI with 64 channel output for dot matrix liquid crystal graphic display systems. This device consists of the display RAM, 64 bit data latch, 64 bit drivers and decoder logic. It has the internal display RAM for storing the display data transferred from a 8 bit micro controller and generates the dot matrix Iiquid crystal driving signals corresponding to stored data. The S6B0108 composed of the liquid crystal display system in combination with the S6B0107 (64 channel common driver). Dot matrix LCD segment driver...

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD Output Register Display On/Off Input Register BLOCK DIAGRAM Instruction Decoder Page Selector Display Start Line Register

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD Chip size: 4090 × 4020 PAD size: 100 × 100 Unit : µm There is mark of S6B0108 on the bottom left in the chip.

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD PAD CENTER COORDINATES PAD Number

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD PIN DESCRIPTION Table 1. Pin Description Pin Number QFP(TQFP) 3(1) 78(76) 73(71), 8(6) Input / Output Description For internal logic circuit (+5V ± 10%) GND (0V) For LCD driver circuit VSS = 0V, VDD = +5V ± 10%, VDD-VEE = 8V - 17V VEE1 and VEE2 is connected by the same voltage. Bias supply voltage terminals to drive the LCD. Chip selection In order to interface data for input or output, the terminals have to be CS1B = L, CS2B = L, and CS3 = H. Alternating signal input for LCD driving. Address control signal to determine the relation between Y address...

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD Table 1. Pin Description (Continued) Pin Number QFP(TQFP) Input / Output Description Read or Write. R/W = H → Data appears at DB<0:7> and can be read by the CPU while E = H, CS1B = L, CS2B = L and CS3 = H . R/W = L → Display data DB<0:7> can be written at falling of E when CS1B = L, CS2B = L and CS3 = H. Data bus. Three state I/O common terminal. LCD segment driver output. Display RAM data 1: On Display RAM data 0: Off (relation of display RAM data & M) Reset signal. When RSTB=L, 93(91) - ON / OFF register becomes set by 0. (display off) – Display...

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD MAXIMUM ABSOLUTE LIMIT Characteristic Operating voltage Supply voltage Operating temperature Storage temperature Driver supply voltage NOTES: 1. Based on VSS = 0V. 2. Applies the same supply voltage to VEE1 and VEE2. VLCD=VDD-VEE. 3. 4. Applies to M, FRM, CL, RSTB, ADC, CLK1, CLK2, CS1B, CS2B, CS3, E, R/W, RS and DB0 - DB7. Applies to V0L(R), V2L(R), V3L(R) and V5L(R). Voltage level: VDD ≥ V0L = V0R ≥ V2L = V2R ≥ V3L = V3R ≥ V5L = V5R

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (VDD = +5V ± 10%, VSS = 0V, VDD-VEE = 8 to 17V, Ta =-30 to +85° C) ° Characteristic Input high voltage Output high voltage Input leakage current Three-state(off) input current Driver input leakage current During display During access Access cycle = 1MHz Operating current NOTES: 1. CL, FRM, M RSTB, CLK1, CLK2 2. CS1B, CS2B, CS3, E, R/W, RS, DB0 - DB7 3. DB0 - DB7 4. Except DB0 - DB7 5. DB0 - DB7 at high impedance 6. V0L(R), V2L(R), V3L(R), V5L(R) 7. 1/64 duty, FCLK = 250kHz, frame frequency = 70HZ, output:...

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD AC CHARACTERISTICS (VDD = +5V ± 10%, VSS = 0V, Ta =-30 to +85° C) ° Clock Timing Characteristic CLK1 "high" level width CLK2 "high" level width Figure 1. External Clock Waveform

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD Display Control Timing Characteristic CL "high" level width Figure 2. Display Control Waveform

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD E high level width Address set-up time Address hold time Data set-up time Data delay time Data hold time (write) Data hold time (read) Figure 3. MPU Write Timing

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD Figure 4. MPU Read Timing

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD OPERATING PRINCIPLES AND METHODS I/O BUFFER Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active mode, Input or output of data and instruction does not execute. Therefore internal state is not change. But RSTB and ADC can operate regardless CS1B-CS3. INPUT REGISTER Input register is provided to interface with MPU which is different operating frequency. Input register stores the data temporarily before writing it into display RAM. When CS1B to CS3 are in the active mode, R/W and RS select the input...

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD RESET The system can be initialized by setting RSTB terminal at low level when turning power on, receiving instruction from MPU. When RSTB becomes low, following procedure is occurred. • Display start line register become set by 0. (Z-address 0) While RSTB is low, No instruction except status read can be accepted. Therefore, execute other instructions after making sure that DB4 = 0 (clear RSTB) and DB7 = 0 (ready) by status read instruction. The Conditions of power supply at initial power up are shown in table 1. Table 2. Power Supply Initial...

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD Busy Flag Busy Flag indicates that S6B0108 is operating or no operating. When busy flag is high, S6B0108 is in internal operating. When busy flag is low, S6B0108 can accept the data or instruction. DB7 indicates busy flag of the S6B0108. Data at address N Busy check Busy check Read data Busy (dummy) check Read data Busy at address check N Data read address N + 1 Busy Check E Busy Flag T Busy fCLK is CLK1, CLK2 frequency Busy Flag

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64CH SEGMENT DRIVER FOR DOT MATRIX LCD Display ON / OFF Flip - Flop The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical low), selective voltage or non selective voltage appears on segment output terminals. When flip-flop is set (logic high), non selective voltage appears on segment output terminals regardless of display RAM data. The display on/off flipflop can changes status by instruction. The display data at all segment disappear while RSTB is low. The status of the flip-flop is output to DB5 by status read instruction. The display...

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