ZL50117 PRODUCT PROFILE - Zarlink Semiconductor - #1

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PRODUCT PREVIEW CESoP PROCESSORS ZL50115/6/7 ZL50115 1 T1 or 1 E1 stream or 1 MVIP/ST-BUS stream at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps (Maximum of 32 DS0 or Nx64 Kbps channels) ZL50116 2 T1 or 2 E1 streams or 2 MVIP/ST-BUS streams at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps (Maximum of 64 DS0 or Nx64 Kbps channels) ZL50117 4 T1 or 4 E1 streams or 1 J2, 1 T3, 1 E3 or 1 STS-1 stream or 4 MVIP/ST-BUS streams at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps .............................................................. ...................................................... ...... .................. ............................ .................... .............. .................. ...... ................................ ............................ ............ .................... ............ ........................ .................. ................ ............................ ............................................ .................................... ...................... ............................ .................................................................................................................................. ............................ ............................ ............................ .................. ........ .................... .............................. ............................ .............. .................. ................ .................. ................ ............ .................. ............ The ZL50117 family of low-density CES-over-Packet processors is a powerful and fl exible method for carrying TDM voice and data traffi c, with associated timing and signaling, across Ethernet, IP, and MPLS networks. Each device provides a fl exible TDM interface with embedded timing solution that fully meets T1/E1 timing and synchronization standards. With an integrated DPLL, internal jitter buffer memory and FE/GE packet interface, the ZL50117 processor family reduces BOM (bill of material) and board space and simplifi es access equipment design. CESoP Processors Expand Reach Flexible TDM access interface supports T1/E1, T3/E3, H.110, H-MVIP and ST-BUS streams Nx64 kbps trunking for traffi c grooming and fractional T1/E1 services Programmable multi-protocol packet encapsulation supports RTP, UDP, Ethernet VLANs, IPv4, IPv6 and MPLS, PWE3 and MEF Circuit Emulation standards Carrier-Grade Voice Quality Support Patented hardware/software techniques for clock recovery and synchronization Advanced QoS mechanism allows traffi c prioritization Extremely low and stable latency, intrinsic delays of <500 ms Embedded Timing Embedded timing recovers clocks across packet networks Per-port T1/E1 clock recovery for asynchronous streams Adaptive clock recovery far exceeding G.823 for E1 and G.824/ T1.403 for T1 timing Dual-reference Stratum 3 DPLL supports TDM H.110 and H-MVIP master and slave timing operation Standard Compliant ITU-T recommendation Y.1413 IETF PWE3 draft standards CESoPSN and SAToP MEF Implementation Agreement for PDH circuits (8.0) MPLS Forum CESoMPLS Implementation Agreement (8.0.0) Customer Support Evaluation boards and API are available, supported by Zarlink’s network of in-house application engineers. Applications Legacy traffi c over PSN TDM over Wi-Fi and WiMAX 3G Wireless Backhaul