ZL50117 PRODUCT PROFILE - Zarlink Semiconductor - #2

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APPLICATION CESoP PROCESSORS ZL50115/6/7 w w w. Z A R L I N K . c o m Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries is believed to be reliable. The products, their specifi cations, services and other information appearing in this publication are subject to change by Zarlink without notice. ZARLINK, ZL, and the Zarlink logo are trademarks of Zarlink Semiconductor Inc. © 2004, Zarlink Semiconductor Inc. All Rights Reserved. Publication Number PP5902 ................ ................ ........ .................... .......... .......... .................... ................ ........................ ................ ............................ ................ ...................... ........................ .......... ................ ........................ .............. .......... ...................... ...................... ............ .............. ............ .......... .......... ...... .......... ................ .................... ...... .............................. ...................................... ........................................ ...................... ........................................ ...................... .......... .................. .............. ............................................ CES-over-Packet technology allows service providers to roll out packet-based access networks, while still providing customers with legacy T1/E1 services. The diagram below shows how the ZL50117 low-density CESoP processor seamlessly emulates TDM traffi c, such as POTS, T1/E1 and fractional T1/E1, across an IP, MPLS or Ethernet network. With Zarlink’s CESoP processors, a wired, wireless or optical packet network infrastructure can deliver converged voice and data services. The TDM interface allows the device to be used directly with Codecs and framers in structured CES mode. In unstructured CES mode, the device interfaces directly to LIUs, providing independent timing recovery for each TDM port. The device supports up to 128 DS0, 4 T1/E1 or 1 J2. The ZL50117 chip ensures high QoS, and supports four classes of service on packet egress for priority treatment of time-sensitive traffi c. When packets are received from the Ethernet network, they are parsed to determine the egress destination, queued based on sequence number, with lost packets fi lled-in to maintain timing integrity. An on-chip per-stream DCO (Digitally Controlled Oscillator) ensures precise synchronization of T1/E1 traffi c across the packet network. Patent-pending software supports adaptive or differential timing so the best scheme can be used for a given application. For added fl exibility, the ZL50117 processor can be confi gured to act as the master or slave timing source using the embedded Stratum 3/4/4E DPLL. The ZL50117 device is equipped with on-board memory that compensates for up to 128 ms of PDV (Packet Delay Variations) in the network, with external support for up to 128 ms. Zarlink offers the industry’s only end-to-end portfolio of circuit- to-packet devices with densities ranging from 1 to 32 T1/E1 (32 to 1024 DS0) streams. The single-chip approach eliminates external circuitry, providing a cost-effective systemlevel solution that saves board space compared to equivalent discrete designs using communications processors. Access Networks