LE57D111 PRODUCT PROFILE - Zarlink Semiconductor - #9

/ 20


catalogue search
P. 01
P. 02
P. 03
P. 04
P. 05
P. 06
P. 07
P. 08
P. 09
P. 10
P. 11
P. 12
P. 13
P. 14
P. 15
P. 16
P. 17
P. 18
P. 19
P. 20
Pages:


See other catalogues for Zarlink Semiconductor

Text version of the page
Le5711
Data Sheet
Logic Output
(Applies to DET1 and DET2.)
Description
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
VOL, Output Low voltage
IOUT = 0.3 mA
0.40
V
VOH, Output High voltage
Iout = -0.1 mA
2.4
Ring-Trip Detector Input
(Applies to DAC, DB1, and DB2.)
Description
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
Bias Current
-500
-50
nA
Common Mode Range
vbat+ 1
-2
V
Detector
Description
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
Off-hook threshold
Active
9
11
On-hook threshold
Active
8.5
10.5
Off-hook threshold
Standby
4
6
mA
On-hook threshold
Standby
3.8
5.8
Hysteresis
0
2
Loop
Notes:
1. Unless otherwise noted, the test conditions are set up by the Le5711 device test circuit as illustrated in Figure 7, on page 14.
2. a. Overload level is defined as THD = 1%.
b. Overload level is defined when THD = 1.5%.
3. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
4. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
5. Group delay can be greatly reduced by using a ZT network such as that shown in Figure 5. The network reduces the group delay to less than 2 and increases 2WRL. The effect of group delay on linecard performance also may be compensated by synthesizing complex impedance with the QLSLAC™ device.
6. Minimum current level guaranteed not to cause a false loop detect.
SLIC Device Decoding
(For i, Channel = 1 or 2)
State
C2i
C1i
Two-Wire Status
DETx output
0
0
0
Disconnect
Ring-Trip Detector
1
0
1
Active
Loop Detector
2
1
1
Polarity Reversed (Le57D111 devices only)
Loop Detector
3
1
0
Standby
Loop Detector
9
Zarlink Semiconductor Inc.

pageCatalog pdf di En 2012-06-22-01