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VRS series - 10 Pages

  1. P. 1

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Catalogue excerpts

Innovative Service Around the Globe YAGEO DATA SHEET SURFACE-MOUNT CERAMIC MULTILAYER CHIP VARISTORS VRS0402/0603 5.5 V TO 38 V RoHS compliant & Halogen Free

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Phfcomp_ Surface-Mount Ceramic MULTILAYER CHIP VARISTORS SCOPE This specification describes chip varistors with lead-free terminations. APPLICATIONS • Consumer electronic equipment • Telecommunications • Notebook • Electronic data processing FEATURES • Excellent clamping voltage • Excellent energy dissipation capability • Quick response time (<1n sec.) • Adjustable capacitance values • High reliability • High transient current capability • Symmetrical voltage-current characteristics ORDERING INFORMATION ° GLOBAL PART NUMBER, PHYCOMP CTC & 12NC All part numbers are identified by the series, size,...

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Phfcomp_Surface-Mount Ceramic MULTILAYER CHIP VARISTORS VR CONSTRUCTION Lead Free terminations, NiSn terminations Surface mount multilayer surge suppressor Very short response time (< 1.0 nsec) Bidirectional clamping Low capacitance for high frequency applications Very low leakage current Table 1 For outlines see fig. 2 TYPE L, (mm) W (mm) T (MM)

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Phfcomp_ Surface-Mount Ceramic MULTILAYER CHIP VARISTORS ELECTRICAL CHARACTERISTICS

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Phfcomp_ Surface-Mount Ceramic MULTILAYER CHIP VARISTORS ELECTRICAL CHARACTERISTICS STANDARD TESTING CONDITION

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Phfcomp_ Surface-Mount Ceramic MULTILAYER CHIP VARISTORS ESD (ELECTROSTATIC DISCHARGE) TEST ESD discharge circuit according to IEC 61000-4-2 SPECIFICATION OF ELECTROSTATIC DISCHARGE (ESD) TEST: According to standard EN 61000-4-2, up to 8 KV direct contact (contact discharge) THICKNESS CLASSES AND PACKING QUANTITY

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Product specification Surface-Mount Ceramic MULTILAYER CHIP VARISTORS METHOD OF MOUNTING For normal use the varistor may be mounted on printed-circuit boards or ceramic substrates by applying wave soldering, reflow soldering (including vapour phase soldering) or conductive adhesive in accordance with CECC 00802 classification A. For advised soldering profiles see Figs 4, 5, and 6. An improper combination of soldering, substrate and chip size can lead to a damaging of the component. The risk increases with the chip size and with temperature fluctuations (>100 °C). More detailed information is available...

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Product specification Surface-Mount Ceramic MULTILAYER CHIP VARISTORS Typical values (solid line) Process limits (dotted lines) The capacitors may be soldered twice in accordance with this method if desired Fig. 5 Double wave soldering Typical values (solid line) Process limits (dotted lines) Fig. 6 Vapour phase soldering

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Phfcomp_ Surface-Mount Ceramic MULTILAYER CHIP VARISTORS TESTS AND REQUIREMENTS Table 5 Test procedures and requirements TEST    TEST METHOD PROCEDURE_ Bond Strength4.9    4.10 To be soldered on the glass-epoxy    No visible damage of Plating on    (thickness 1.6 mm), the load shall be put on End Face    the board bends 1 mm Solderability 4.10 4.11 Unmounted chips completely immersed for The termination should be well tinned 2 ±0.5 seconds (dipping time) in a solder bath at 235 ±2 °C Resistance to4.10.2    4.12 Solder bath temperature: 260 ±5 °C    | A V1mA / V1mA | <10% Soldering Heat    Dipping...

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