Xilinx Quad Flat No-Lead (QFN) package - Xilinx - #1

XAPP439 (v1.0) April 11, 2005

Summary Xilinx Quad Flat No-Lead (QFN) package is a robust and low profile leadframe-based plastic

package that has several advantages over traditional leadframe packages.The exposed die attach paddle enables efficient thermal dissipation when directly soldered to the PCB. Additionally, this near chip scale package offers improved electrical performance, smaller package size, and an absence of external leads. Since the package has no external leads, coplanarity and bent leads are no longer a concern.

For QFN package to perform at the peak, special considerations are required to properly assemble the package and design the PCB. For optimal thermal, electrical, and board level performance, the exposed pad on the package should be soldered to the board using a corresponding thermal pad on the board. Also, for proper heat conduction through the board, the thermal pad region of the PCB should contain thermal vias.

The following factors have major effect on the quality and reliability of assembling QFN packages: PCB pad pattern design, amount of solder paste in thermal pad region, stencil design, type of solder paste, and reflow profile. This application note provides a good guideline on PCB pad pattern design and assembling of QFN packages for optimal reliability and quality. This is only a guideline and users are encouraged to perform actual studies to optimize the process.

Figure 1 below shows the PCB pad pattern dimensions to be determined. The dimension X and Y indicate the width and length of the pad. CLL and CPL define the clearances needed to avoid solder bridging. CLL defines the minimum distance between land to land for the corner joints on adjacent sides and CPL defines the minimum distance between the inner tip of the peripheral lands and the outer edge of the thermal pad. CLL should be 0.1 mm and CPL should be 0.15mm.

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CLL

CPL

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Y 1

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X

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I I I I I I

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NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

XAPP439 (v1.0) April 11, 2005

PCB Pad Pattern Design... 1