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Virtex-5 Family Overview - 34458 Virtex-5 Family Overview
DS100 (v5.0) February 6, 2009
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Product Specification
General Description
The Virtex®-5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL™ (AdvancedSilicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choiceoffered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logicdesigns. In addition to the most advanced, high-performance logic fabric, Virtex-5FPGAs contain many hard-IP system level blocks,including powerful 36-Kbit block RAM/FIFOs, second generation 25x18 DSP slices, SelectIO™ technology with built-in digitally-
controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tileswith integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options.
Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity,PCIExpress® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance
PowerPC®440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of
performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength
of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSPdesigners, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and
connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and
link/transaction layer capability.
Summary of Virtex-5 FPGA Features
Five platforms LX, LXT, SXT, TXT, and FXT Advanced DSP48E slices
Virtex-5 LX: High-performance general logic applications 25x18, two’s complement, multiplication Virtex-5 LXT: High-performance logic with advanced serial connectivity Optional adder, subtracter, and accumulator Optional pipelining Virtex-5 SXT: High-performance signal processing applications with advanced serial connectivity Optional bitwise logical functionality Dedicated cascade connections Virtex-5 TXT: High-performance systems with double density advanced serial connectivity
Flexible configuration options
SPI and Parallel FLASH interface Virtex-5 FXT: High-performance embedded systems with advanced serial connectivity Multi-bitstream support with dedicated fallback reconfiguration logic
Cross-platform compatibility
Auto bus width detection capability LXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulators
System Monitoring capability on all devices Most advanced, high-performance, optimal-utilization, FPGA fabric
On-chip/Off-chip thermal monitoring On-chip/Off-chip power supply monitoring Real 6-input look-up table (LUT) technology JTAG access to all monitored quantities Dual 5-LUT option
Integrated Endpoint blocks for PCI Express Designs
Improved reduced-hop routing LXT, SXT, TXT, and FXT Platforms 64-bit distributed RAM option Compliant with the PCI Express Base Specification 1.1 SRL32/Dual SRL16 option x1, x4, or x8 lane support per block Works in conjunction with RocketIO™ transceivers
Powerful clock management tile (CMT) clocking
Digital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shifting
Tri-mode 10/100/1000 Mb/s Ethernet MACs
LXT, SXT, TXT, and FXT Platforms RocketIO transceivers can be used as PHY or connect to external PHY using many soft MII (Media Independent Interface) options PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division
36-Kbit block RAM/FIFOs RocketIO GTP transceivers 100Mb/s to 3.75Gb/s
True dual-port RAM blocks LXT and SXT Platforms Enhanced optional programmable FIFO logic
RocketIO GTX transceivers 150Mb/s to 6.5Gb/s
Programmable TXT and FXT Platforms - True dual-port widths up to x36
PowerPC 440 Microprocessors
- Simple dual-port widths up to x72 FXT Platform only Built-in optional error-correction circuitry RISC architecture Optionally program each block as two independent 18-Kbit blocks 7-stage pipeline 32-Kbyte instruction and data caches included
High-performance parallel SelectIO technology
Optimized processor interface structure (crossbar) 1.2 to 3.3V I/O Operation
65-nm copper CMOS process technology
Source-synchronous interfacing using ChipSync™ technology
1.0V core voltage High signal-integrity flip-chip packaging available in standard or Pb-free package options
Digitally-controlled impedance (DCI) active termination Flexible fine-grained I/O banking High-speed
memory interface support
© 2006–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PowerPC is a trademark of IBM Corp. and is used under license. PCI, PCIExpress, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.
DS100 (v5.0) February 6, 2009www.xilinx.com
Product Specification1
