Tensilica's Xtensa LX2 processor - Tensilica - #1

• Highly efficient, small, low-power base 32-bit modern architecture

- Configurable over a wide range of options -get just what you need

- Configure processor as a multi-issue VLIW using FLIX™ architecture

• Extend processor with application-specific instructions, execution units, and register files

• Unlimited I/O bandwidth with designer-defined FIFO, GPIO, and Lookup interfaces

• Automated fine-grained clock gating for ultra-low power

• Designer-selectable 5- or 7-stage pipeline depth

• Automatic synthesis of processor configurations and extensions with XPRES™ Compiler

• Local memories configurable up to 4MB with the option for parity or ECC

• Modelessly intermix 24-bit base ISA instruc­tions with 16-bit narrow instructions and VLIW instructions

Implement hardware architecture equivalent to RTL- based hardware design, with dramatically faster design time and much lower verification effort

High bandwidth data flow through processor with flexible I/O interfaces that bypass the sys­tem bus

Quickly and easily scale hardware architecture by simply using more task-customized processors

Lower verification effort with pre-verified, correct-by-construction RTL generation

Post-silicon programmability

Higher code density due to 24-bit ISA leads to savings in memory area

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Xtensa LX2 Configurable Processor Core

Tensilica's Xtensa® LX2 processor core has two essential unique features: configurability and extensibility. These features enable Xtensa processors to be used as an application-specific processor by software developers and as an RTL alternative by hardware designers. Ideal for handling traditional SOC embedded proces­sor control tasks as well as compute-intensive datapath hardware tasks, the Xtensa LX2 proces­sor is the new basic building block for complex SOC design.