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| Datasheet | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| TetraMAX ATPG Automatic Test Pattern Generation | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Overview TetraMAX® ATPG automatically generates high quality manufacturing test vectors. TetraMAX is the only ATPG solution optimized for a wide range of test methodologies that's integrated with Synopsys' DFT MAX, the leading test synthesis tool. The unparalleled ease-of-use and high performance provided by TetraMAX allows RTL designers to quickly create efficient, compact tests for even the most complex designs. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Key Benefits • Increases product quality with generated test vectors for high defect detection • Reduces testing costs through the use of advanced vector compaction techniques • Increases designer productivity by leveraging integration with Synopsys DFT MAX • Creates tests for complex and multi-million gate designs Key Features • Extremely high capacity and performance • Integrated graphical user interface • Integrated simulation waveform viewer • Integrated context-sensitive online help • Comprehensive scan design rule checking • Utilizes existing Verilog simulation libraries • DSMTest option supports testing for timing-related deep submicron defects • IddQTest option available for quiescent test validation • Integrated fault simulator for functional vectors • Distributed Processing runs across multiple processors • Yield Diagnostics with automatic defect isolation • DSMTest option supports testing for timing-related deep-submicron defects, including small delay defects Testing Complex ASICs AXI Master and slave interfaces for inbound and outbound PCI With TetraMAX ATPG, designers can generate high quality manufacturing test vectors without compromising on highperformance design techniques. While such techniques may impede older generation ATPG tools, TetraMAX is able to obtain coverage on the resulting complex logic. | TetraMAX supports internal three-state busses including implementations with pull-ups, pull-downs and charge storage. Similar to three-state busses, bidirectional I/O pads are also supported. To ensure ATE (automatic test equipment) requirements are met, TetraMAX provides a number of options to generate contention-free vectors for three-state logic. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DFT MAX | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| RTL TestDRC Full-Scan DFT AutoFix | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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| TetraMAX | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| High-Performance ATPG | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Integrated GUI | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Fault Simulator | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Test Vectors | Te st Reports | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Figure 1: Integrated Test Flow Using TetraMAX ATPG | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||